Overall Block Diagram; Shutter (1 - Sony DSLR-A900 Service Manual

3. BLOCK DIAGRAMS

3-1. OVERALL BLOCK DIAGRAM (1/6)

IS-030 BOARD
CN5002
(SHUTTER)
W8 21
IC5004
V8 20
CMOS
IMAGER
B9 47
C10 45
B10 44
C9 46
A10 42
D9 49
C8 50
X5001
54MHz
W16
SHUTTER
UNIT
CN5001
TH5001
5
CN4508
1C_MAG SH_1C
2
2C_MAG SH_2C
3
X_ON
1
CONTROL
BLOCK
SREL(-) SHUTTER_RELEASE_MG-
XSC_CAM_1
15
XSC_CAM_2
16
CN4518 IC4402 , Q4412 - Q4414
SCM+ SC_M+
M M
SHUTTER CHARGE
1
M901
SHUTTER CHARGE
MOTOR
CN4525
ACT901 MREL(-) MIRROR_RELEASE_MG-
2
ACTUATOR
CN4509
MCM+ MC_M+
1
M M
MCM- MC_M-
2
M902
MIRROR CHARGE
MOTOR
AFM-003
FLEXIBLE
BOARD
MIRROR CHARGE
(1/2)
CN4512
CAM DETECT
(1/2)
xMC_CAM_1 XMC_CAM_1
5
xMC_CAM_2 XMC_CAM_2
7
05
DSLR-A900_L2
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
FP-894 FLEXIBLE AM-015 BOARD (1/6)
BOARD
CN3102
DP00 - DP11
DM00 - DM11
DPCK
21
DMCK
20
SDO
47
SDI
45
SCK
44
XCE
46
XCLR
42
XHS
49
XVS
50
FP-893 FLEXIBLE
BOARD
CN3101
IMG_TEMP1 CMOS_TEMP_1
47
1ST_CURTAIN_MG
2
STAR_SI_AS
STAR_SO_AS
OVERALL (4/6)
STAR_SCK_AS
(PAGE 3-4)
STAR_CS_AS
Q4409
1ST_CURTAIN_MG
T7
SHUTTER
2ND_CURTAIN_MG
DRIVE
U7
XSHUTTER_X_SW
T11
Q4411
SHUTTER SHUTTER_RELEASE_MG
T10
RELEASE
XSC_CAM_1
N11
XSC_CAM_2
N14
SHUTTER_CHARGE_M_1
T6
SHUTTER_CHARGE_M_2
U6
MOTOR DRIVE
(18/26)
IC4001
(1/5)
MAIN CPU
Q4410
(16/26)
MIRROR MIRROR_RELEASE_MG
U10
RELEASE
MIRROR_CHARGE_M_1
IC4401
18 N6
MIRROR CHARGE
MOTOR DRIVE MIRROR_CHARGE_M_2
19 P6
(18/26)
XMC_CAM_1
P11
XMC_CAM_2
B14 B5
M14
CF_TEMP
D6
XCF_IN_CA
1 B3 M4
XMSX_IN_CA
A3 L1
OVERALL (2/6)
XHDMI_HPD_IN
B2 M2
(PAGE 3-2)
XCABLE_IN
D2 M1
CMOS_SLVDS_DP[00-11]
CMOS_SLVDS_DN[00-11]
CMOS_SLVDS_CLKP
A16
CMOS_SLVDS_CLKN
A17
CMOS_SI
E8
CMOS_SO
E6
CMOS_SCK
E9
XCMOS_CE
F9 IC1001
(1/2)
XCMOS_CLR
D3 IMAGE
PROCESSOR
1
XCMOS_HS
B8
(1/26 - 6/26)
XCMOS_VS
B7
NZ_DDR2_D[00-07] NZ_DDR2_D[00-31]
IC1201 NZ_DDR2A_A[00-13], NZ_DDR2A_BA[0-2]
1G NZ_DDR2A_XCS
G8 W33
SDRAM
NZ_DDR2A_CKE
F2 W30
(5/26)
NZ_DDR2A_CLK
E8 Y35
NZ_DDR2A_XCLK
F8 W35
NZ_DDR2_D[08-15]
IC1203
1G NZ_DDR2A_XCS
G8
SDRAM
NZ_DDR2A_CKE
F2
(5/26)
NZ_DDR2A_CLK
E8
NZ_DDR2A_XCLK
F8
NZ_DDR2_D[16-23]
IC1202 NZ_DDR2B_A[00-13], NZ_DDR2B_BA[0-2]
1G NZ_DDR2B_XCS
G8 AL34
SDRAM
NZ_DDR2B_CKE
F2 AM34
(5/26)
NZ_DDR2B_CLK
E8 AL35
NZ_DDR2B_XCLK
F8 AK35
NZ_DDR2_D[24-31]
IC1204
1G NZ_DDR2B_XCS
G8
SDRAM
NZ_DDR2B_CKE
F2
(5/26)
NZ_DDR2B_CLK
E8
NZ_DDR2B_XCLK
F8
STAR_SI_AS
N5
STAR_SO_AS
L2
STAR_SCK_AS
L1
STAR_CS_AS
L3
3
XLENS_RELEASE_SW_IMG
C4
OVERALL (3/6)
(PAGE 3-3)
E_1ST_CURTAIN_START
P2
CAP_CTRL_IN
B4
STAR_SI_CA
M5
STAR_SO_CA
K2
STAR_SCK_CA
K1
STAR_CS_CA
K3
3-1
E1_RIF_D[00-15]
E1_RIF_CLK
A25 AF5
XE1_RIF_HD
E23 AF9 E1_DDR2_D[00-31]
XE1_RIF_VD
F23 AC11
E1_DDR2_A[00-12], E1_DDR2_BA0, E1_DDR2_BA1
W25
E1_JIF_D[00-15] U24
V26
U26
E1_JIF_ACK
B32 W23
STAR_SI_E1
B34 D1
STAR_SO_E1
B33 D3
STAR_SCK_E1
A32 E1
STAR_CS_E1
A33 C4
XE1_RST
F13 B25
E1_BOOT IC2001
E13 AE2
(1/2)
E1_SPU_EN
F12 AF11
IMAGE
NZ_REL_EN_E1
E12 AC8
PROCESSOR
E1_CAP_START
2
E11 B1
(7/26 - 9/26)
IMG_SYSCLK_12M
AG1 A18
B6
3 6 AF7
IC2102
X1001
CLOCK
12MHz
GENERATOR 4 F3
(7/26)
8 G2
XIMG_RESET
K6
IMG_SYSCLK_12M_E2
A18
E2_RIF_D[00-15]
B6
E2_RIF_CLK
D35 AF5
XE2_RIF_HD
D34 AF9 E2_DDR2_D[00-31]
XE2_RIF_VD
D33 AC11
E2_DDR2_A[00-12], E2_DDR2_BA0, E2_DDR2_BA1
W25
E2_JIF_D[00-15] U24
V26
U26
E2_JIF_ACK
J33 W23
IC2401
STAR_SI_E2
E22 D1
IMAGE
STAR_SO_E2
F21 D3 PROCESSOR
STAR_SCK_E2
3
G21 E1
STAR_CS_E2 (11/26 - 13/26)
E21 C4
XE2_RST
C10 B25
E2_BOOT
E10 AE2
E2_SPU_EN
F10 AF11
NZ_REL_EN_E2
F11 AC8
XUPDATE_LED_ON
AP4
D1001
(F/W UPDATE)
NZ_EMC_D[00-15]
IC1501
NZ_EMC_A[00-22]
XNZ_EMC_CS 64M FLASH
Y5 G1
(6/26)
NZ_EMC_CLK
V1 A3
XNZ_EMC_RESET
AA6 C4
E1_DDR2_D[00-15]
IC2003
XCS_DDR2_E1
512M
L8
SDRAM
E1_DDR2_CKE
K2
(8/26)
E1_DDR2_CLK
J8
XE1_DDR2_CLK
K8
E1_DDR2_D[16-31]
IC2002
XCS_DDR2_E1
512M
L8
SDRAM
E1_DDR2_CKE
K2
(8/26)
E1_DDR2_CLK
J8
XE1_DDR2_CLK
K8
E1_SYS_D[00-15]
IC2201
E1_SYS_A[01-22]
32M FLASH
XCS_SYS_E1
(10/26)
F1
XIMG_RESET
B4
4
XIMG_RESET
OVERALL (6/6)
(PAGE 3-6)
E2_SYS_D[00-15]
IC2601
E2_SYS_A[01-22]
32M FLASH
XCS_SYS_E2
(14/26)
F1
XIMG_RESET
B4
E2_DDR2_D[00-15]
IC2403
XCS_DDR2_E2 512M
L8
SDRAM
E2_DDR2_CKE
K2
(12/26)
E2_DDR2_CLK
J8
XE2_DDR2_CLK
K8
E2_DDR2_D[16-31]
IC2402
XCS_DDR2_E2
512M
L8
SDRAM
E2_DDR2_CKE
K2
(12/26)
E2_DDR2_CLK
J8
XE2_DDR2_CLK
K8
A : VIDEO SIGNAL