Panasonic CQ-C8305U Service Manual page 13

Pin Port Description
No.
93 SUB_RESE Reset for display CPU
T
94 DISPM_CO 5V power control for
NT Display
95 NC Not connected
96 NC Not connected
11.2. Display Block
IC901:YEAM30879FL
Pin. Port
No.
1 UART_SS4 GND
2 UART_SS3 GND
3 D_DIS Disable for Anode drive (Disable
for image signal)
4 PADJ2 Anode output pulse width
adjusting data 2(image data)
5 DCLK_SLV3 Slave D-CLK 3(Clock for image
data)
6 BUS_BYTE GND
7 PMOD_CHG CPU rewrite mode/Single CPU mode
selection for Flash writer
8 IADJ Anode output current adjusting
data(Luminance control)
9 I_CLK Clock for anode output current
adjusting data
10 RESET Reset for Main CPU
11 XOUT Ceramic oscillator clock(8Mhz)
12 GND GND
13 XIN Ceramic oscillator clock(8Mhz)
14 VCC5_0V Power supply
15 NMI Pulled up to H
16 Y_SYNC Cathode scan data and cathode
latch control (Vertical sync)
17 ROTARY_A Volume-up detection from Rotary
encoder
18 ROTARY_B Volume-down detection from
Rotary encoder
19 X_SYNC Clock for Cathode scan ; or
Latch strobe for Anode output
pulse width adjusting data and
Anode output current adjusting
data
20 A_CLK_TA Anode output pulse width
adjusting clock
21 A_CLK_SCLK Anode pulse width adjustment
clock signal UART5
22 A_CLK Anode pulse width adjustment
clock signal UART5
23 S_DIS Disable for Cathode drive
24 NC
25 OEL_RESET OEL RESET Output
26 NC
27 SUB_SI CPU communication data output
28 SUB_SO CPU communication data input
29 PADJ1(TxD) Anode output pulse width
adjustment data signal 1 (image
data)UART1
30 _( R ) (D) NC
31 DCLK_MST Master D-CLK (Clock for image
data)UART1
32 UART_SS4?BUS GND
Y?
33 OEL_OE OEL Outopttoinabl output
34 PADJ0 Anode output pulse width
adjustment data signal 0 (image
data)UART0
35 DCLK_SLV0 Slave D-CLK 0 (Clock for image
data)
36 UART_SS0 GND
37 RDY CPU RDY
38 FLASH_RESET Reset for Flash memory
39 HOLD EPM Program mode enable for Flash
writer
40 FLASH_WP Write protect/Accelaration from
Flash memory
41 FLASH_CE Chip enable for Flash memory
I/O FM AM
O 5.1 5.1 5.1
O/I 0 0
O 0 0
O 0 0
Description I/O (V)
I
I
O
O
I
I
I
O
O
I
O
_
I
_
I
O
I
I
O
I
O
O
_
O
_
I
O
O
O/I
O
O
O
O
I
I
I
O
I
O
O
CD Pin Port
No.
97 NC Not connected
98 S_LED Security LED drive
0
99 ANT_CONT Power control for antenna
motor
0
100 NC/EP_CS Not connected
0
Pin. Port
No.
42 FLASH_OE Output enable for Flash memory
43 NC
0
44 FLASH_WE Write enable for Flash
0
45 NC
4.7
46 FLASH_A22 A21 in Address bus
47 FLASH_A21 A20 in Address bus
4.7
48 FLASH_A20 A19 in Address bus
49 FLASH_A19 A18 in Address bus
4.5
50 FLASH_A18 A17 in Address bus
0
51 FLASH_A17 A16 in Address bus
0
52 FLASH_A16 A15 in Address bus
53 FLASH_A15 A14 in Address bus
5
54 FLASH_A14 A13 in Address bus
55 FLASH_A13 A12 in Address bus
5
56 FLASH_A12 A11 in Address bus
57 FLASH_A11 A10 in Address bus
4.6
58 FLASH_A10 A9 in Address bus
3.7
59 FLASH_A9 A8 in Address bus
0
60 VDD 3.3V +3.3v Power supply
3.7
61 FLASH_A8 A7 in Address bus
5
62 GND GND
5
63 FLASH_A7 A6 in Address bus
4.7
64 FLASH_A6 A5 in Address bus
65 FLASH_A5 A4 in Address bus
0
66 FLASH_A4 A3 in Address bus
0 67 FLASH_A3 A2 in Address bus
68 FLASH_A2 A1 in Address bus
4.7
69 FLASH_A1 A0 in Address bus
70 FLASH_RY/BY Pulled up to H
71 FLASH_D15 DQ15 in Data bus
72 FLASH_D14 DQ14 in Data bus
73 FLASH_D13 DQ13 in Data bus
4.7
74 FLASH_D12 DQ12 in Data bus
4.7
75 FLASH_D11 DQ11 in Data bus
76 FLASH_D10 DQ10 in Data bus
4.7
77 FLASH_D9 DQ9 in Data bus
78 FLASH_D8 DQ8 in Data bus
4.7
79 FLASH_D7 DQ7 in Data bus
0
80 FLASH_D6 DQ6 in Data bus
5
81 FLASH_D5 DQ5 in Data bus
0
82 FLASH_D4 DQ4 in Data bus
4.8
83 FLASH_D3 DQ3 in Data bus
4.8
84 FLASH_D2 DQ2 in Data bus
4.7
85 FLASH_D1 DQ1 in Data bus
86 FLASH_D0 DQ0 in Data bus
87 KEY_RET4 Key return 4
0
88 KEY_RET3 Key return 3
4.7
89 KEY_RET2 Key return 2
0
90 KEY_RET1 Key return 1
91 KS3 Key scan 3
0
92 KS2 Key scan 2
4.7
93 KS1 Key scan 1
94 AD_AVSS A/D converter grand potential
95 TH_DETECT Temperature detection input
4.7
96 AD_VREF +5v Power supply
97 AD_AVCC +5v Power supply
0
98 PADJ3 Anode output pulse width
3.7
adjustment data signal 3 (image
3.7
data)UART4
3.7
99 NC
100 DCLK_SLV4 Slave D-CLK 4 (Clock for image
3.7
data)
0
13
Description I/O FM
O 0
O 0
O 5.1
I 0
Description
CQ-C8305U
AM CD
0 0
0 0
5.1 5.1
0 0
I/O (V)
O 4.8
_ 4.8
O 3.7
_ 3.7
O 4.5
O 4.5
O 4.5
O 4.5
O 4.5
O 4.5
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
_ 3.8
O 4.7
_ 0
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
O 4.7
I 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I/O 4.7
I 0
I 0
I 0
I 0
I/O 4.7
I/O 4.7
I/O 4.7
_ 0
I 2
_ 5
_ 5
O 4.7
_ 0
I 4.7