B03C, Umac 1 Ddr3 - Philips 40PFL8008K/12 Service Manual

Circuit Diagrams and PWB Layouts
10-1-12

B03C, Umac 1 DDR3

Umac 1 DDR3
B03C
+1V5-M1
M1-MA0
3J18 3J19
M1-MA1 100R 100R
3J1B
3J1A
100R 100R
M1-MA2
3J1C 3J1D +1V5-M1
100R 100R
M1-MA3
3J1E 3J1F
M1-MA4 100R 100R
3J1H
3J1G
100R 100R
M1-MA5
3J1J 3J1K
100R 100R
M1-MA6
3J1M
3J1L
100R 100R
M1-MA7
3J1N 3J1P
100R 100R
M1-MA8
3J1Y 3J1R
M1-MA9 100R 100R
FJ08
3J1T
3J1S
DDR-MVREF11
100R 100R
M1-MA10
3J1U 3J1V
100R 100R
M1-MA11
3J1Z
3J1W
100R 100R
M1-MA12
3J20 3J21
100R 100R
M1-MA13
3J22 3J23
M1-MA14 100R 100R
3J25
3J24
M1-MCLK0
100R 100R
M1-MA15
3J26 3J27
100R 100R +1V5-M1
M1-BA0
3J29
3J28
100R 100R
M1-BA1
3J2A 3J2B
100R 100R
M1-BA2
RES
3J2C 3J2D
M1-RAS# 100R 100R
3J2F
3J2E
100R 100R
M1-CAS#
3J2G 3J2H
100R 100R
M1-WE#
3J2K
3J2J
100R 100R
M1-CS#
3J2L 3J2M
100R 100R
M1-ODT
3J2N 3J2P
M1-CKE 100R 100R M1-MCLK0#
3J2R
3J2Q
100R 100R
M1-RESET#
3J2S 3J2T
100R 100R
QFU1.2E LA 10.
+1V5-M1
7J01
H5TQ2G63BFR-PBC
VDD
N3
M1-MA0
0
P7
M1-MA1
1
P3
M1-MA2
2
M1-MA3 N2
3
P8
M1-MA4
4
P2
M1-MA5
5
R8 A
M1-MA6
6
R2
M1-MA7
7
M1-MA8 DB31 T8
8
R3
M1-MA9
9
L7
M1-MA10
10
DB32 R7
M1-MA11
11
N7
M1-MA12
12
M1-MA13 DB33 T3
13
DB34 T7
M1-MA14
14
M7
M1-MA15
15
BC
AP
H1
DDR-MVREF11
VREFDQ
M8
VREFCA
L8
ZQ
M2
BA0
N8
BA1
DB62 M3
BA2
M1-BA0 J3
RAS
DB90 K1
M1-BA1
ODT
DB35 K3
M1-BA2
CAS
DB36 J7
M1-RAS#
CK
DB38 K7
M1-ODT
CK
M1-CAS# K9
CKE
M1-MCLK0 DB91 L2
CS
DB39 L3
M1-MCLK0#
WE
T2
RESET
M1-CKE DB92 E7
DML
M1-CS# D3
DMU VSS
M1-WE#
M1-RESET#
M1-DQM1
M1-DQM0
+1V5-M1
+1V5-M1
EN 70
VDDQ
D7 M1-MD1
0
C3
M1-MD4
1
C8
DB40 M1-MD3 M1-MA0
2
C2
M1-MD6 M1-MA1
3
DQU A7 M1-MD5 M1-MA2
4
A2 M1-MD0
M1-MA3
5
B8
M1-MD7 M1-MA4
6
A3
DB41 M1-MD2 M1-MA5
7
M1-MA6
C7 DB42 M1-DQS0 M1-MA7
DQSU
B7 DB43 M1-DQS#0
M1-MA8
DQSU
M1-MA9
F3
DB44 M1-DQS1 M1-MA10
DQSL
G3
DB45 M1-DQS#1 M1-MA11
DQSL
M1-MA12
E3 M1-MD14
M1-MA13
0
F7
M1-MD15 M1-MA14
1
F2
M1-MD12 M1-MA15
2
F8
M1-MD11
3
DQL H3 M1-MD8
4
H8 DB48 M1-MD9
5
G2
M1-MD10 DDR-MVREF12
6
H7
M1-MD13
7
DB63
J1
J9
NC L1
M1-BA0
L9
M1-BA1
M1-BA2
M1-RAS#
M1-ODT
VSSQ M1-CAS#
M1-MCLK0
M1-MCLK0#
M1-CKE
M1-CS#
M1-WE#
M1-RESET#
M1-DQM3
M1-DQM2
DDR-MVREF12
+1V5-M1
DB93 DB98
DB94 DB99
DB95 DB01
DB96 DBA1
DB97 DBA2
+1V5-M1
back to
2014-Jan-10
div. table
+1V5-M1
7J02
H5TQ2G63BFR-PBC
VDD VDDQ
N3
0
P7
1
P3
2
N2
3
P8
4
P2
5
R8 A
6
DB49 R2
7
DB50 T8
8
R3
9
L7
10
R7
11
N7
12
DB51 T3
13
DB52 T7
14
M7
15
BC
AP
H1
VREFDQ
M8
VREFCA
L8
ZQ
M2
BA0
N8
BA1
M3
BA2
DB64
DB53 J3
RAS
K1
ODT
K3
DB54
CAS
J7
CK
K7
CK
K9
CKE
L2
CS
L3
DB55
WE
T2
RESET
DBA8
E7
DML
D3
DMU VSSQ
VSS
DB66
+1V5-M1
FJ09
DBA3
DBA4
DBA5
DBA6
DBA7
Umac 1 DDR3
B03C
D7
M1-MD21
0
C3
DB56 M1-MD22
1
C8
M1-MD23
2
C2 M1-MD16
3
DQU A7
M1-MD17
4
A2
M1-MD18
5
B8
DB57 M1-MD19
6
A3
M1-MD20
7
C7
M1-DQS2
DQSU
B7
M1-DQS#2
DQSU
F3
DB58 M1-DQS3
DQSL
G3 DB59 M1-DQS#3
DQSL
E3
M1-MD28
0
F7
M1-MD31
1
F2
M1-MD30
2
F8 M1-MD27
3
DQL H3
M1-MD26
4
H8
M1-MD25
5
G2
M1-MD24
6
H7
M1-MD29
7
DB65
J1
J9
NC L1
L9
4 2012-11-22
3104 313 6612
19370_138_130227.eps
130227