Sharp lc-42ad5e Service Manual page 75

2.9. IC4201/IC4202 (RH-iXB742WJZZQ)
2.9.1 Block Diagram
2.9.2 Pin Connections and short description
Pin No. Pin Name
38 CLK
19 CS
37 CKE
23 A0
24 A1
25 A2
26 A3
29 A4
30 A5
31 A6
32 A7
33 A8
34 A9
22 A10
35 A11
20, 21 BA0, BA1
18 RAS
I/O
I Active on the positive going edge to sample all inputs.
I Disables or enables device operation by masking or enabling all inputs except CLK, CKE and
DQM.
I Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
I Row/column addresses are multiplexed on the same pins.
Row address: RA0-RA11,
I
Column address: CA0-CA7
I
I
I
I
I
I
I
I
I
I
I Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
I Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
5 – 18
Pin Function
LC-42AD5E/RU/S