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3 7 63 1515 0
Pin No.
Pin Name
141
PIO [10:0]
142, 143
VDATA [7:0]
144
VDD
145
VDATA [7:0]
146
VSS
147
PIO [10:0]
148
VDATA [7:0]
149
VDD
150
VDATA [7:0]
151
VSS
152
VDATA [7:0]
153
PIO [10:0]
154, 155
VDATA [7:0]
157
HSYNC
TE
L 13942296513
158
VSYNC
160
VDD
161
DA-DATA
162
VSS
166
DA-LRCK
167
DA-BCK
168
VDD
169
DA-XCX
170
VSS
171
DAI-DATA
172
DAI-LRCK
173
DAI-BCK
174
PIO [10:0]
175
VDD
176
A-VDD
www
177
VCLK
178
SYSCLK
.
179
A-VSS
180
CD-DATA
181
VDD
58
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I/O
I/O
Programmable I/O pins.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
—
3.3-V supply voltage for core logic and I/O signals.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
—
Ground for core logic and I/O signals.
I/O
Programmable I/O pins.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
—
3.3-V supply voltage for core logic and I/O signals.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
—
Ground for core logic and I/O signals.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
I/O
Programmable I/O pins.
O
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the
decoder does not drive VDATA. During boot-up, the decoder uses configuration
parameters to drive or 3-state VDATA.
I/O
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after
the falling (active) edge of HSYNC.
I/O
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the
first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH=Bottom field. VSYNC LOW=Top field)
—
3.3-V supply voltage for core logic and I/O signals.
O
Serial audio samples relative to DA-BCK clock.
—
Ground for core logic and I/O signals.
O
PCM left-right clock. Identifies the channel for each audio sample. The polarity is
programmable.
O
PCM bit clock. Divided by 8 from DA-XCX, DA-BCK can be either 48 or 32 times the
sampling clock.
—
3.3-V supply voltage for core logic and I/O signals.
I/O
Audio external frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK
can be either 384 or 256 times the sampling frequency.
—
Ground for core logic and I/O signals.
I
PCM input data, two channels. Serial audio samples relative to DA-BCK clock,
resulting in downmixed audio output.
I
PCM input left-right clock.
I
PCM input bit clock.
I/O
Programmable I/O pins.
—
3.3-V supply voltage for core logic and I/O signals.
—
3.3-V analog supply voltage.
I
Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.
I
System clock. Decoder requires an external 27 MHz TTL oscillator. Drive with the
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same 27-MHz as VCK.
i
—
Analog ground for PLL.
I
Serial CD data.
—
3.3-V supply voltage for core logic and I/O signals.
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2 9
8
Function
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3
6 7
1 3
1 5
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9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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