Motorola ONCE SC140 Application Note page 24

/* EOnCE registers */
#define EXCP_TABLE 0x7000
#define REG_BASE_ADDRESS 0x00effe00
#ifdef COMPILER_BETA_1_BUG
long EE_CTRL
long EDCA1_CTRL
long EDCA1_REFA
long EDCA1_REFB
long EDCA1_MASK
long ECNT_CTRL
long ECNT_VAL
long ECNT_EXT
#else
#define EMCR
#define ERCV
#define ETRSMT0
#define ETRSMT1
#define EE_CTRL
#define PC_EX
#define EDCA0_CTRL
#define EDCA1_CTRL
#define EDCA2_CTRL
#define EDCA3_CTRL
#define EDCA4_CTRL
#define EDCA5_CTRL
#define EDCA0_REFA
#define EDCA1_REFA
#define EDCA2_REFA
#define EDCA3_REFA
#define EDCA4_REFA
#define EDCA5_REFA
#define EDCA0_REFB
#define EDCA1_REFB
#define EDCA2_REFB
#define EDCA3_REFB
#define EDCA4_REFB
#define EDCA5_REFB
#define EDCA0_MASK
#define EDCA1_MASK
#define EDCA2_MASK
#define EDCA3_MASK
#define EDCA4_MASK
#define EDCA5_MASK
#define EDCD_CTRL
#define EDCD_REF
#define EDCD_MASK
#define ECNT_CTRL
#define ECNT_VAL
#define ECNT_EXT
#define ESEL_CTRL
#define ESEL_DM
#define ESEL_DI
#define ESEL_RST
#define ESEL_ETB
#define ESEL_DTB
#define TB_CTRL
#define TB_RD
#define TB_WR
#define TB_BUFF
#define TRAP_EXCP
#define ILL_EXCP
#define DBG_EXCP
#define OVFL_EXCP
#define AUTO_NMI_EXCP
#define AUTO_EXT_EXCP
#define NMI_EXCP
#define EXT_EXCP
#endif
A-2
Code A-2. EOnCE_registers.h
= REG_BASE_ADDRESS+0x18; /* EOnCE EE pins Control register */
= REG_BASE_ADDRESS+0x44; /* EOnCE EDCA #1 Control register */
= REG_BASE_ADDRESS+0x64; /* EOnCE EDCA #1 Reference Value A */
= REG_BASE_ADDRESS+0x84; /* EOnCE EDCA #1 Reference Value B */
= REG_BASE_ADDRESS+0xc4; /* EOnCE EDCA #1 Mask Register */
= REG_BASE_ADDRESS+0x100; /* EOnCE Counter Control register */
= REG_BASE_ADDRESS+0x104; /* EOnCE Counter Value register */
= REG_BASE_ADDRESS+0x108; /* EOnCE Extension Counter Value */
REG_BASE_ADDRESS+0x4 /* EOnCE Monitor and Control register */
REG_BASE_ADDRESS+0x8 /* EOnCE Receive register */
REG_BASE_ADDRESS+0x10 /* EOnCE Receive register */
REG_BASE_ADDRESS+0x14 /* EOnCE Receive register */
REG_BASE_ADDRESS+0x18 /* EOnCE EE pins Control register */
REG_BASE_ADDRESS+0x1c /* EOnCE Exception PC register */
REG_BASE_ADDRESS+0x40 /* EOnCE EDCA #0 Control register */
REG_BASE_ADDRESS+0x44 /* EOnCE EDCA #1 Control register */
REG_BASE_ADDRESS+0x48 /* EOnCE EDCA #2 Control register */
REG_BASE_ADDRESS+0x4c /* EOnCE EDCA #3 Control register */
REG_BASE_ADDRESS+0x50 /* EOnCE EDCA #4 Control register */
REG_BASE_ADDRESS+0x54 /* EOnCE EDCA #5 Control register */
REG_BASE_ADDRESS+0x60 /* EOnCE EDCA #0 Reference Value A */
REG_BASE_ADDRESS+0x64 /* EOnCE EDCA #1 Reference Value A */
REG_BASE_ADDRESS+0x68 /* EOnCE EDCA #2 Reference Value A */
REG_BASE_ADDRESS+0x6c /* EOnCE EDCA #3 Reference Value A */
REG_BASE_ADDRESS+0x70 /* EOnCE EDCA #4 Reference Value A */
REG_BASE_ADDRESS+0x74 /* EOnCE EDCA #5 Reference Value A */
REG_BASE_ADDRESS+0x80 /* EOnCE EDCA #0 Reference Value B */
REG_BASE_ADDRESS+0x84 /* EOnCE EDCA #1 Reference Value B */
REG_BASE_ADDRESS+0x88 /* EOnCE EDCA #2 Reference Value B */
REG_BASE_ADDRESS+0x8c /* EOnCE EDCA #3 Reference Value B */
REG_BASE_ADDRESS+0x90 /* EOnCE EDCA #4 Reference Value B */
REG_BASE_ADDRESS+0x94
REG_BASE_ADDRESS+0xc0
REG_BASE_ADDRESS+0xc4
REG_BASE_ADDRESS+0xc8
REG_BASE_ADDRESS+0xcc
REG_BASE_ADDRESS+0xd0
REG_BASE_ADDRESS+0xd4
REG_BASE_ADDRESS+0xe0
REG_BASE_ADDRESS+0xe4
REG_BASE_ADDRESS+0xe8
REG_BASE_ADDRESS+0x100
REG_BASE_ADDRESS+0x104
REG_BASE_ADDRESS+0x108
REG_BASE_ADDRESS+0x120
REG_BASE_ADDRESS+0x124
REG_BASE_ADDRESS+0x128
REG_BASE_ADDRESS+0x12c
REG_BASE_ADDRESS+0x130
REG_BASE_ADDRESS+0x134
REG_BASE_ADDRESS+0x140
REG_BASE_ADDRESS+0x144
REG_BASE_ADDRESS+0x148
REG_BASE_ADDRESS+0x14c
EXCP_TABLE
EXCP_TABLE+0x80 /* illegal set or illegal instruction exception */
EXCP_TABLE+0xc0
EXCP_TABLE+0x100
EXCP_TABLE+0x180
EXCP_TABLE+0x1c0
EXCP_TABLE+0x280
EXCP_TABLE+0x2c0
Using the SC140 Enhanced OnCE Stopwatch Timer
/* EOnCE Status register */
/* EOnCE EDCA #5 Reference Value B */
/* EOnCE EDCA #0 Mask Register */
/* EOnCE EDCA #1 Mask Register */
/* EOnCE EDCA #2 Mask Register */
/* EOnCE EDCA #3 Mask Register */
/* EOnCE EDCA #4 Mask Register */
/* EOnCE EDCA #5 Mask Register */
/* EOnCE EDCD Control register */
/* EOnCE EDCD Reference Value */
/* EOnCE EDCD Mask register */
/* EOnCE Counter Control register */
/* EOnCE Counter Value register */
/* EOnCE Extension Counter Value */
/* EOnCE Selector Control register */
/* EOnCE Selector DM Mask */
/* EOnCE Selector DI Mask */
/* EOnCE Selector RST Mask */
/* EOnCE Selector ETB Mask */
/* EOnCE Selector DTB Mask */
/* EOnCE Trace Buffer Control register */
/* EOnCE Trace Buffer Read Pointer */
/* EOnCE Trace Buffer Write Pointer */
/* EOnCE Trace Buffer */
/* trap instruction exception */
/* debug exception (eonce) */
/* overflow exception */
/* default nmi exception vector */
/* default external exception */
/* nmi exception vector (arbitrary address) */
/* external exception (arbitrary address) */