Block Diagram - Main Section - Sony CDX-737 Service Manual

Q Q
3 7 6 3 1 5 1 5 0
7-2. BLOCK DIAGRAM – MAIN Section –
PCMD, BCK,
LRCK, WDCK
PCMD DATI
(Page 16) A 11
BCK
BCKI
9
LRCK
LRCI DSP
12
INTERFACE
WDCK WDCI
13
DIN
4
RFCK, GTOP, WFCK,
C4M, XROF RFCK RFCK
(Page 16) B
7
GTOP GTOP
8
WFCK WFCK
3
DATA
C4M C4M
5 LINKING
XROI
XROF
CONTROL
6
SCOR SCOR
(Page 16) G
61
RESET
(Page 16) H
2 XRST
1
DATA, CLOCK
F
(Page 16)
T E
L 1 3 9 4 2 2 9 6 5 1 3
25
76 SCOR
WFCK
77
SCLK
D
(Page 16) 8 SCLK
IC503
SBSO
E
(Page 16) 9 SSI
ADD0 – ADD14
11 – 18, 64 – 69, 74
10 – 3, 25, 24, 21, 23, 2, 26, 1
A0 – A14
w w w
05
.
http://www.xiaoyu163.com
D-RAM CONTROLLER
IC401
D OUT
DIGITAL
20
OUT
DATA
D/A 18
BCK
CONVERTER
SELECTOR 17
LRCK
INTERFACE
19
D-RAM INTERFACE
XTAI
TIMING
16
GENERATOR
READ/WRITE
BASE VWA
A0 – A9
COUNTER
ADDRESS MONITOR
CPU INTERFACE
D1 – D4
XRAS
60 47 48 46 50 45 44 49 59
28
XCAS
34
XWE
29
XOE
35
46 29 27 41 42 28 26
79 78 77 76 74
7 6 5 4 56
RST 28
CD TEXT DECODER
IC501
BUCK 78
DATA0 – DATA7
20 – 27 62 63 30 29
X501
10MHz
11 – 13, 15 – 19 20 27
DO0 – DO7
S-RAM
IC502
x a o u 1 6 3
y
i
http://www.xiaoyu163.com
8 9
DIGITAL FILTER, D/A CONVERTER,
LOW-PASS FILTER
IC601
DATA
∆Σ
22 DIGITAL
SERIAL
BCK
FILTER MODULATOR
23 INPUT
LRCK
CIRCUIT CIRCUIT
INTERFACE
24
TIMING CPU
GENERATOR INTERFACE
MCK
13 OSC
16 15 21
D-RAM
IC402
X601
16.9344MHz
4
XRAS
23
XCAS
3
XWE
22
XOE
Q Q
3 7 6 3 1 5
45
SYSTEM CONTROLLER
IC201 (2/3)
75
D501
c o
.
17 17
2 4 2
9 8
• SIGNAL PATH
: CD PLAY
CN901 (1/2)
AUDIO OUT
LO
9
LOW-PASS
FILTER
RO
MUTING
5
Q610
MUTING
Q620
19
MUTING
CONTROL SWITCH
Q601, 602
C16M
C
1 5 0 8 9 2 4 9 8
44 43
RESET
I
BU CHECK
J
m
CDX-737
9 9
L
R
(Page 16)
2 9 9
(Page 18)
(Page 18)