Theory Of Operation; Video - Samsung cea455 series Service Manual

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THEORY OF OPERATION
GENERAL
CEA4551 is a high resolution color display using a
0.31 dot pitch NON-GLARE CRT. (CEA4552 ; 0.39
glare CRT,CEA4553 ; 0.39 non-glare CRT, CEA4554
; 0.41 glare CRT , CEA4555 ; 0.41 non-glare CRT)
It uses R, G, B, I or R, r, G, g, B, b TTL input Video
Signals and separate TTL sync signals.lt can operate
in 16 colors 640 by 200 overscan mode or 64colors
640 by 350 underscan mode. This two mode Is
automatically switched by the polarity of vertical
frequency.
VIDEO
I. Video Drive Circuit
The video signals are applied to CUSTOM IC
(IC1 01). The output signals of IC101 are applied
to IC103 which is an open-collector Hex-buffer.
The output signal level of IC103 (R,r,G,g,B,b)
are controlled by the BRIGHTNESS VR and
SUB-BRIGHTNESS VR (VR110) and the secon-
dary signals (r, g, b) are controlled by the
CONTRAST VA.
The output signals of IC103 are to combine
blanking signals (H, V blanking).
Primary signals (R, G, B) and secondary signals
(r, g, b) are mixed through R121 and D116,R123
and D117,R125 and D115 respectively in mode
2.Then the signals are applied to the base of
pre-amp transistors(0103,0104,0105).
The output signals of IC101 in MODE 1 and
MODE 2 are selected by the MODE signal from
pin no.8 of IC101 (SL205).
2. VIDEO (R, G, B) OUTPUT
The R,G,B drive system is utilized in the video
output circuit of this unit.
In the case of RED signal,the combined color
and blanking signals are amplfied sufficiently by
the cascode transistor (0109, 0110)
The cut-off levels of the picture tube are con-
trolled by the bias VRs (VR103,VR1 04,VR1 05)
between 85Vdc and 145Vdc.
These DC voltages are taken from pin no.8 of
FBT (T 403) and pin no.14 of POWER TRANS
(T601).
The color signals and blanking signals of 0103,
0104 and 0105 are supplied to the base of
0110, 0112, 0114.
The screen grid, G2, is common in the case of
RED,GREEN and BLUE CATHODE respectively.
The drive control VRs (VR101, VR102) control
the base current of 0110, 0114 for white balance
adjustment.
FIG. 2 SYNC INTERFACE CIRCUIT
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