Xc-Is21Md - Pioneer XC-IS21 MD Servise Manual

XC-IS21MD

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Pin Function
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Pin Name I/O
o.
SubQ 80-bit, PCM peak and level data output
1 SQSO O
CD TEXT data output
2 SQCK I Clock input for SQSO readout
3 XRST I System reset
4 SYSM I Mute input
5 DATA I Serial data input from CPU
Latch input from CPU
6 XLAT I
Serial data is latched at the falling edge.
7 CLOK I Serial data transfer clock input from CPU
8 SENS O SENS output to CPU
9 SCLK I Clock input for SENS serial-data readout
−
10 V Digital power supply
DD
11 ATSK I/O Input and output for unti-shock
12 SPOA I Microcomputer extended interface (input A)
13 SPOB I Microcomputer extended interface (input B)
14 XLON O Microcomputer extended interface (output)
15 WFCK O WFCK output
XUGF output
16 XUGF O
switching the command.
XPLCK output
17 XPCK O
command.
GFS output
18 GFS O
switching the command.
C2PO output
19 C2PO O
command.
Outputs "H" when either subcode sync. S0 or S1 is
20 SCOR O
detected.
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21 COUT I/O Input and output of track-number count signal
22 MIRR I/O Mirror signal input and output
23 DFCT I/O Defect signal input and output
24 FOK I/O Focus OK signal input and output
GFS is sampled at 460Hz;when GFS is "H", this pin
25 LOCK I/O outputs "H". If GFS is "L" eight consecutive
samples, this pin outputs "L". Input when LKIN="H".
26 MDP O Servo control output of spindle motor
27 SSTP I Detection signal input of disc innermost
28 SFDR O
Sled drive output
29 SRDR O
30 TFDR O
Tracking drive output
31 TRDR O
32 FFDR O
Focus drive output
33 FRDR O
−
34 V Digital GND
SS
35 TEST I
TEST pin : normally GND
36 TEST I
Crystal selector input
37 XTSL I
"L":16.9344MHz , "H":33.8688MHz
38 VC I Center voltage input
39 FE I Focus error signal input
40 SE I Sled error signal input
Notes) www
• PCMD is an MSB first. two's complement output.
• GTOP is used to monitor the frame sync protection status. (High:sync protection window released)
• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.
.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
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Function
Reset when "L"
Mute when "H"
MNT1 and RFCK output by
MNT0 output by switching the
MNT3 and XRAOF output by
GTOP output by switching the
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No. Pin Name I/O
41 TE I Tracking error input
42 CE I Center servo analog input
43 RFDC I RF signal input
44 ADIO O OP amplifier output
−
45 AV 0 Analog GND
SS
46 IGEN I Constant current input for OP amplifier
−
47 AV 0 Analog power supply
DD
48 ASYO O EFM full-swing output ("L"=VSS, "H"=VDD)
49 ASYI I Asymmetry comparate voltage input
50 BIAS I Constant current input of the asymmetry circuit
51 RFAC I EFM signal input
−
52 AV 3 Analog GND
SS
53 CLTV I VCO control voltage input for master
54 FILO O Filter output for master PLL (Slave=digital PLL)
55 FILI I Filter input for master PLL
56 PCO O Charge pump output for master PLL
−
57 AV 3 Analog power supply
DD
−
58 V Digital GND
SS
−
59 V Digital power supply
DD
60 DOUT O DIGITAL OUT output
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61 LRCK O D/A interface
D/A interface
62 PCMD O
Serial data output (two's complement, MSB first)
63 BCK O D/A interface Bit clock output
Outputs "H" when the playback disc has emphasis,
64 EMPH O
and "L" when there is no emphasis.
−
65 XV Power supply for master clock
DD
Crystal oscillation circuit input
66 XTAI I
Input the external master clock via this pin.
67 XTAO O Crystal oscillation circuit output
−
68 XV GND for master clock
SS
−
69 AV 1 Analog power supply
DD
70 AOUT1 O L ch analog output
71 AIN1 I L ch OP amp. input
72 LOUT1 O L ch LINE output
−
73 AV 1 Analog GND
SS
−
74 AV 2 Analog GND
SS
75 LOUT2 O R ch LINE output
76 AIN2 I R ch OP amp. input
77 AOUT2 O R ch analog output
−
78 AV 2 Analog power supply
DD
79 RMUT O R ch zero detection flag
80 LMUT O L ch zero detection flag
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Function
0 5 8 2 9 9 4 2 8
LR clock output f=Fs
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