AOpen AX45-8X Online Manual page 106

A X 4 5 - 8 X / A X 4 5
A X 4 5 - 8 X / A X 4 5
P B S R A M ( P i p e l i n e d
P B S R A M ( P i p e l i n e d
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address decoding time
and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks, which is
faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and Socket 370 CPU do not need
PBSRAM.
P C - 1 0 0 D I M M
P C - 1 0 0 D I M M
SDRAM DIMM that supports 100MHz CPU
P P C C - - 1 1 3 3 3 3 D D I I M M M M
SDRAM DIMM that supports 133MHz CPU
P C - 1 6 0 0 o r P C - 2 1 0 0
P C - 1 6 0 0 o r P C - 2 1 0
Based on FSB frequency, the DDR DRAM has 200MHz and 266MHz two type of working frequency. Because of DDR DRAM data bus is
64-bit, it provides data transfer bandwidth up to 200x64/8=1600MB/s, and 266x64/8=2100MB/s. Hence, the PC-1600 DDR DRAM is
working with 100MHz and PC-2100 DDR DRAM is working with 133MHz FSB frequency.
P P C C I I ( ( P P e e r r i i p p h h e e r r a a l l C C o o m m
Bus for the internal connection of peripheral devices, high-speed data channel between the computer and expansion card.
- 8 X N
- 8 X N
B u r s t S R A M )
B u r s t S R A M )
FSB bus clock.
FSB bus clock.
D D R D R A M
0 D D R D R A M
p p o o n n e e n n t t I I n n t t e e r r f f a a c c e e ) ) B B u u s s
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