Sanyo DC-TS780 Service Manual page 29

IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36748(DVD Player AV Decorder)
Pin No.
172
(DAC B)
173
(DAC C)
170 CVBS/C
(DAC D)
175
Digital video port, CPU and ADP test (8 pin)
199 VID[7]#
ICETMS#
GPCI/O[22]
201 VID[6]#
ICETDI#
GPCI/O[23]
200 VID[5]#
ICETDO#
GPCI/O[24]
198 VID[4]#
ICETCK#
GPCI/O[25]
202
JTCK#
GPCI/O[46]
203 VID[2]#
JTMS#
GPCI/O[47]
205 VID[1]#
PUPRD
204 VID[0]#
JTDO#
PUPTD
Digital audio port (11 pin)
179 AMCLK
181 S/PDIF
186,187 AOUT[2:1]
184 AOUT[0]
192
188 ALRCLK
190 ABCLK
182 GPAI/O
162 GCLK1
193 PLLCFGA#
GPCI/O[21]
Name I/O
Y/R/V AO YC O : Y signal O.
RGB O : R signal O.
YUV O : V signal O.
C/B/U AO YC O : C signal O.
RGB O : B signal O.
YUV O : U sibnal O.
AO Which CVBS signal or C signal O.
Select be unrelated to YC / RGB / YUV mide.
RSET AI DAC adjusting resistor connect.
O# ITU-R656 conform Y / C multiplex digital video O.
I# ADP ICE interface modo select I.
I/O Controled general I / O by microcomputer software.
O# ITU-R656 conform Y / C multiplex digital video O.
I# ADP ICE interface data I.
I/O Coutroled general I / O by microcomputer software.
O# ITU-R656 conform Y / C multiplex digital video O.
O# ADP ICE interface data O.
I/O Controled general I / O by microcomputer software.
O# ITU-R656 conform Y / C multiplex digital video O.
I# ADP ICE interface clock I.
I/O Controled general I / O by microcomputer software.
VID[3] O# ITU-R656 conform Y / C multiplex digital video O.
I# CPU JTAG clock I.
I/O Controled general I / O by microcomputer software.
O# ITU-R656 conform Y / C multiplex digital video O.
I# CPUJTAG tms I.
I/O Controled general I / O by microcomputer software.
O# ITU-R656 conform Y / C multiplex digital video O.
JTDI# I# CPUJTAG data I.
I Probe UART data I.
O# ITU-R656 conform Y / C multiplex digital video O.
O# CPUJTAG data O.
O Probe UART data O.
I/O Audio master clock I / O.
128,192,256 or 384fs sampling frequency (Programable) use.
O S / PDIF O.
N / C
O Digital stereo audio serial data O.
AIN I Digital stereo audio serial data I.
Digital stereo audio bit clock O.
O
Palarity is programable.
O Digital stereo audio LR clock O.
AOUT and AIN data output or latch, clock trailing edge or
last transition edge(programable).
Controled general I / O by ADP software.
I/O
ID 27.000MHz clock I for audio master clock generating.
Connected to GCLK when usually operation.
ID# Audio PLL set I.
Can change when RESET# signal assert.
Uqually operation : low RESET# signai assert term.
I/O Controled general I / O by microcomputer softwaer.
Function
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