Sony HDR-HC3 Service Manual page 26

3-1. OVERALL BLOCK DIAGRAM (1/7)
CM-071 BOARD
LENS BLOCK
IRIS
(SHUTTER)
IC7601
2M CMOS
IMAGER
SE7701
YAW SENSOR
SE7702
PITCH SENSOR
LD-202 BOARD (1/3)
IRIS
CN7103
METER
I_DRIVE±
M
I_BIAS±
H
I_HALL±
ND FILTER
METER
ND_DRIVE±
M
ND_BIAS±
H
ND_HALL±
FOCUS
IC7201
FOCUS ±
MOTOR
M
NOISE FILTER
(1/2)
F_MR_A,
FOCUS MR F_MR_B
SENSOR
ZOOM_A,
ZOOM_B,
ZOOM
Z00M_XA,
IC7202 IC7203
MOTOR ZOOM_XB
M
NOISE FILTER
(1/2)
Z_MR_A,
Z_MR_B
ZOOM MR
SENSOR
NF MOTOR
NF_DRIVE±
M
TEMP_OUT
LENS TEMP
23
SENSOR
MOTOR UNIT
(LENS BARRIER)
CN7102
COVER_DRIVE+,
M001
COVER_DRIVE-
M M
LENS COVER
MOTOR
IC001
COVER_CLOSE
2 6
LENS COVER
COVER_OPEN
OPEN/CLOSE 3 5
SENSOR
05
HDR-HC3/HC3E/HC3K/HC3EK_L2
3. BLOCK DIAGRAMS
( ) : Number in parenthesis ( ) indicates the division number of schematic diagram where the component is located.
VC-441 BOARD (1/7)
CN7501 CN1004
DRVOUT1_RB1, DCOUT1_RB1,
DRVOUT1_RB1, DCOUT1_RB1,
DRVOUT4_GG1, DCOUT4_GG1 DRVOUT4_GG1, DCOUT4_GG1
DRVOUT2_RB2, DCOUT2_RB2,
DRVOUT2_RB2, DCOUT2_RB2,
DRVOUT5_GG2, DCOUT5_GG2
DRVOUT5_GG2, DCOUT5_GG2
DRVOUT3_RB3, DCOUT3_RB3, DRVOUT3_RB3, DCOUT3_RB3,
DRVOUT6_GG3, DCOUT6_GG3
DRVOUT6_GG3, DCOUT6_GG3
CHCK
23 1 1
IC7502
TGHD_BO,
TGVD_BO 7, 5 1, 3
XSYS_RST_BO 2 6
27 20 20
AHS_SO_BO,
AHS_SCK_BO,
IC7501
XCS_AHS_BO
2, 5, 7 6, 3, 1
YAW_AD YAW_AD
10 16 23 23
IC7701
PITCH/YAW
SENSOR
PITCH_AD PITCH_AD
20
6
AMP 24 24
VST_C_RESET VST_C_RESET
17 22 22
FP-409
IC7204
FLEXIBLE
(1/2)
CN7105 CN1019
BOARD (1/3)
(1/3) (1/3)
PNDCK
K12 11 35
CAM_VD
IRIS
L12 22 24
DRIVE,
HALL
AMP
C9
I_HALL_AD
A4 2 44
A10
ND_HALL_AD
D10 1 45
ND
FILTER
DRIVE,
HALL
AMP
2 F3
FOCUS
MOTOR
XCS_IC_7204
DRIVE J12 18 28
XRST_IC_7204
H11 23 23
2
ZOOM
EN1, DIRA1, DIRB1
MOTOR
DRIVE
NF_EN, NF_SW
NF MOTOR
DRIVE
LENS_TEMP_AD
9 37
IC7301
LENS_COVER_DIR_PWM, LENS_COVER_DRV_ON
LENS COVER
MOTOR DRIVE
(1/2)
LENS_COVER_CLOSE
24 22
LENS_COVER_OPEN
25 21
AD0_0 - AD0_13
AD1_0 - AD1_13
AD2_0 - AD2_13
CHCK
ADC_SO, ADC_SCK, ADC_XCS0
IC1301
CDS,
CLPOB
A/D H5
TGHD, TGVD
CONVERTER
ADC_TGHD, ADC_TGVD
(1/17)
XSYS_RST
XSYS_RST
D6
CAM_VD_HS
D7
CHCK
K5
A_2.8V
IC1402
1 5
CLOCK
X1401
GENERATOR
80.9191 MHz : NTSC
(2/17)
62.3700 MHz : PAL
AHS_SO, AHS_SCK, AHS_XCS0
TG_FLD
J1
D13
CAM_VD_HS
K1
D7
A7
YAW_AD
P23
PITCH_AD
P22
VST_C_RESET
T2
P20
F2
F4
CAM_SI, CAM_SO, CAM_SCK, XCS_IC_7204
ZOOM_SW_AD
M22
SIRCS_SIG
C22
IC4801 A10
NTSC/XPAL_DET
B14
A17
CAMERA
SYS_V
CONTROL B8
(12/17)
XSLOWSHUT_NR
B13
HI_SI, HI_SO, XHI_SCK
R22
XCS_CAMERA
AC6
C1
20MHz
D1
XCS_EEP_C
F1
D5
EEP_SI_C,
EEP_SO_C,
B5
EEP_SCK_C
3-1
IC1401
R1
CAMERA
SIGNAL
K21
PROCESSOR
(2/17)
128M SDRAM
SD_CK
A3
AHS_TGHD, AHS_TGVD
SD_XCS
A10
CHCK
U1
AB4
XSYS_RST
T4
PNDCK
AC11
EN1, DIRA1, DIRB1
CAM_VD
AC7
CAM_VD_HS
AA6
TG_FLD
L21
XCS_IC_1401_BUS
AA3
IC_1401_BUS_CLK
AC5
F23
H22
D24A00_CAM - D31A07_CAM,
DXXA08_CAM - DXXA13_CAM
XSYS_RST
X4801
IC4803
1
128k EEPROM
(12/17)
HDI_Y0 - HDI_Y7
HDI_C0 - HDI_C7
HDI_HD, HDI_VD, HDI_OE
VCK
U1
IC1601
IC1801
(1/5)
(2/17)
BASE BAND
A8, B9, B8, C9, H7, H8, J8, J7, SIGNAL
C8, D9, D8, E9, J3, J2, H3 - H1, PROCESSOR
E1, D2, D1, C2, G3, H9, G2, G7,
(3/17)
F2 G9 C1, B2, B1, A2 G8
AE23
V22
SD_DQ0 - SD_DQ15
SD_A0 - AD_A11, SD_BA0, SD_BA1
STROBE_ON
EXT_STROBE_ON
XSYS_RST OVERALL (7/7)
1
(PAGE 3-7)
ZOOM_SW_AD
SIRCS_SIG
NTSC/XPAL_DET
SYS_V
SYS_V
OVERALL (4/7)
2
XSLOWSHUT_NR
(PAGE 3-4)
HI_SI, HI_SO, XHI_SCK
OVERALL (5/7)
3
(PAGE 3-5)
XCS_CAMERA
A
: VIDEO SIGNAL