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2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
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Low power mode This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep mode and deep sleep mode in the Cortex -M0+ processor, respectively. ® Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL xiii (Rev. 1.1)
Instruction cache 512 bytes HW processor (HWP) Sound play function Sound algorithm EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format) Playback channels 2 channels with mixing supported (e.g. Ch.0: voice, Ch.1: BGM) Sampling frequency 15.625 kHz...
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Reset when the watchdog timer overflows (can be enabled/disabled using a register). Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/dis- abled using a register). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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-M0+ processor. The RAM retains data even in SLEEP mode. ® *3 HALT mode refers to sleep mode in the Cortex -M0+ processor. ® *4 Shown in parentheses are JEITA package names. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Connection Diagram” chapter, respectively. DDQSPI is the power supply dedicated for the quad synchronous serial interface (QSPI-Flash). It is also used as DDQSPI the power supply for the I/O ports P60 to P65. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
(Set to automatic mode) 5. Switch the system clock to a high-speed clock. 6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note, however, that the software reset operations depend on the periph- eral circuit. For more information, refer to “Control Registers” in each peripheral circuit chapter. Note: The MODEN bit of some peripheral circuits does not issue software reset. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
OSC1 crystal oscillator circuit Unavailable Available Available OSC1 internal oscillator circuit Available Available Available OSC2 crystal/ceramic oscillator circuit Available Available Available OSC3 internal oscillator circuit Available Available Available EXOSC clock input Available Available Available Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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OSC3 pin open. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Figure 2.3.4.2 shows an operation example when the oscillation start- up control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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CLGOSC1.INV1B[1:0], and CLGTRIM2.OSC1SAJ[5:0] bits should be determined after performing evaluation using the populated circuit board. Note: Make sure the CLGOSC.OSC1EN bit is set to 0 (while the OSC1 oscillation is halted) when set- ting the CLGTRIM2.OSC1SAJ[5:0] bits. Seiko Epson Corporation 2-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-11...
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OSC1CLK clock generated by the OSC1 oscillator circuit (crystal oscillator). However, this function is effective only when 16 MHz (CLGOSC3.OSC3FQ[1:0] bits = 0x3) has been selected to the OSC3 oscillation frequency. Seiko Epson Corporation 2-12 S1C31D41 TECHNICAL MANUAL...
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7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current (I OSD1 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-13 (Rev. 1.1)
0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this mode when no software processing and peripheral circuit operations are required, power consumption can be less than HALT mode. The RAM retains data even in SLEEP mode. Seiko Epson Corporation 2-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-15 (Rev. 1.1)
These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-17 (Rev. 1.1)
This bit selects an oscillator type of the OSC1 oscillator circuit. 1 (R/WP): Internal oscillator 0 (R/WP): Crystal oscillator Bits 10–8 CGI1[2:0] These bits set the internal gate capacitance in the OSC1 oscillator circuit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-19 (Rev. 1.1)
0 (R/W): Disable external output Note: Since the FOUT signal generated is out of sync with writings to the CLGFOUT.FOUTEN bit, a glitch may occur when the FOUT output is enabled or disabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-23...
“Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation 2-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
“Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC3 oscillator circuit is inactive. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 2-25 (Rev. 1.1)
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Architecture Reference Manual ® 2. Cortex -M0+Technical Reference Manual ® 3. Cortex -M0+ Devices Generic User Guide ® These documents can be downloaded from the document site of Arm Ltd. https://developer.arm.com/documentation Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Notes: • When programming the Flash memory, 2.2 V or more V voltage is required. • Be sure to avoid using the V pin output for driving external circuits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that. Program example: FLASHC->WAIT_b.RDWAIT = 1; asm(“NOP”); asm(“NOP”); CLG->OSC_b.IOSCEN = 0; Seiko Epson Corporation 4-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
CPU even if the interrupt flag is set to 1. An interrupt request is also sent to the CPU if the status is changed to interrupt enabled when the interrupt flag is 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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DMA transfer for the channel with the highest priority. If the arbitration cycle setting value is larger than the number of successive data transfers, successive data trans- fers will not be suspended. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 6-11 (Rev. 1.1)
The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 6-13 (Rev. 1.1)
Pd[3:0] Total number of ports 25 ports 39 ports 55 ports Ports for debug function Pd[1:0] Key-entry reset function Unavailable *1 Ports with general-purpose I/O function (GPIO) *2 Ports with interrupt function Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status (PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock source. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PPORTPxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PPORTPxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
7.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
CPU only when the interrupt flag, of which interrupt has been enabled by the in- terrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL...
When both data output and data input are enabled, the pin output status controlled by this IC can be read. These bits do not affect the input control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
These bits select the input signal edge to generate a port input interrupt. 1 (R/W): An interrupt will occur at a falling edge. 0 (R/W): An interrupt will occur at a rising edge. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
These bits select the peripheral I/O function to be assigned to each port pin. Table 7.6.1 Selecting Peripheral I/O Function PPORTPxFNCSEL.PxyMUX[1:0] bits Peripheral I/O function Function 3 Function 2 Function 1 Function 0 This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
1/32,768 1/16,384 1/8,192 1/4,096 1/2,048 1/1,024 1/512 1/256 1/128 1/64 1/32 1/16 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation 7-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 7-11 (Rev. 1.1)
4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDT2CMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
* Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-1...
3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-3...
10.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31D41 TECHNICAL MANUAL...
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-5...
1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-7 (Rev. 1.1)
10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-9 (Rev. 1.1)
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
These bits are used to set and read day of the week. The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 10-11...
EXSVD0 EXSEL External voltage selector Voltage SVDDT EXSVD1 comparator circuit VDSEL Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To CPU Figure 11.1.1 SVD3 Configuration Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-1 (Rev. 1.1)
If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 11-2 S1C31D41 TECHNICAL MANUAL...
SVD3CTL.MODEN bit = 1, wait for at least SVD circuit response SVD_EXT time before reading the SVD3INTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-3 (Rev. 1.1)
SVDIF bit). An interrupt request is sent to the CPU only when the SVD3INTF.SVDIF bit is set while the interrupt is enabled by the SVD3INTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 11-4 S1C31D41 TECHNICAL MANUAL (Rev.
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-5 (Rev. 1.1)
0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 11-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
, EXSVDn) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V , EXSVDn) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Bits 7–1 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 11-7 (Rev. 1.1)
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
If the port is shared with the EXCLm pin and other functions, the EXCLm input function must be assigned to the port before using the event counter function. The EXCLm signal can be input through the chattering filter. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-1...
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-3...
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 12-7 (Rev. 1.1)
(Clock source selection) - UART3_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
(UART3_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART3_nMOD.PREN bit UART3_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-3 (Rev. 1.1)
8. Configure the DMA controller and set the following UART3 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART3_nTBEDMAEN and UART3_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31D41 TECHNICAL MANUAL...
Read the UART3_nINTF.TBEIF bit UART3_nINTF.TBEIF = 1 ? Write transmit data to the UART3_nTXD register Transmit data remained? Wait for an interrupt request (UART3_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-5 (Rev. 1.1)
UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31D41 TECHNICAL MANUAL...
Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-7...
When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-9 (Rev.
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-10 S1C31D41 TECHNICAL MANUAL...
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1 (R/W): Enable parity function 0 (R/W): Disable parity function Bit 1 PRMD This bit selects either odd parity or even parity when using the parity function. 1 (R/W): Odd parity 0 (R/W): Even parity Seiko Epson Corporation 13-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: If the UART3_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART3_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART3_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 13-13...
This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation 13-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-3...
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-5...
Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-7 (Rev. 1.1)
Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-9 (Rev. 1.1)
• Slave mode starts data transfer when SPICLKn is input from the external SPI master after the #SPISSn signal is asserted. Writing transmit data is not a trigger to start data transfer. Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Seiko Epson Corporation 14-10 S1C31D41 TECHNICAL MANUAL...
1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-11 (Rev. 1.1)
SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31D41 TECHNICAL MANUAL...
These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 14-15 (Rev. 1.1)
Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31D41 TECHNICAL MANUAL...
To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit timer channel are set (1 or 0). Seiko Epson Corporation 15-6 S1C31D41 TECHNICAL MANUAL...
Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHDL[3:0] bits = 0x7, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31D41 TECHNICAL MANUAL...
(QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-9...
Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to the QSPI_ nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 15-12 S1C31D41 TECHNICAL MANUAL...
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DMA transfer in advance so that transmit data will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-13...
TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. Seiko Epson Corporation 15-14 S1C31D41 TECHNICAL MANUAL...
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DMA controller and dummy data is transferred from the specified memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-15...
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DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the next data. 13. Wait for a DMA interrupt. Seiko Epson Corporation 15-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
If the address in the memory mapped access area that is continuous to the previous read address is read when the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system bus with the HREADY signal held high (zero-wait read). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-17...
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Data cycle 3 QSPI_nMOD register Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-19 (Rev. 1.1)
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HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Dummy cycle Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-21 (Rev. 1.1)
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HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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Address cycle Dummy cycle Data cycle (low-order 16 bits) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-23 (Rev. 1.1)
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The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-24 S1C31D41 TECHNICAL MANUAL...
1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-25...
Data (W) → QSPI_nTXD Software operations QSPI_nRXD → Data (R) QSPI_nRXD → Data (R) Figure 15.5.9.1 Example of Data Transfer Operations in Slave Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) Seiko Epson Corporation 15-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in reg- ister access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-27...
When a 32-bit data is prefetched into the FIFO When the FIFO read access FIFO data FIFO data ready flag in memory mapped access mode level is cleared to 0 ready (internal signal) Seiko Epson Corporation 15-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. Bits 11–8 CHLN[3:0] These bits set the number of clocks for data transfer. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-29 (Rev. 1.1)
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0 (R/W): MSB first Bit 2 CPHA Bit 1 CPOL These bits set the QSPI clock phase and polarity. For more information, refer to “QSPI Clock (QSPI- CLKn) Phase and Polarity.” Seiko Epson Corporation 15-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-31...
Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-33 (Rev. 1.1)
Flash memory in the memory mapped access mode. This setting is re- quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-35...
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The QSDIOn[3:0] pins are used. Dual transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Single transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Seiko Epson Corporation 15-36 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us- ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 15-37...
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 16-2 S1C31D41 TECHNICAL MANUAL...
16.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-3 (Rev. 1.1)
- Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 16-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-5...
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Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 16.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 16-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
10. (When DMA is not used) Repeat Steps 6 to 8 until the end of data reception. 11. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-7...
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S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 16-8 S1C31D41 TECHNICAL MANUAL...
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Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-9 (Rev. 1.1)
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 16-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-11...
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A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 16-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-13...
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Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 16.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 16-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-15...
4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 16-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-19 (Rev. 1.1)
STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 16-20 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 16-21 (Rev. 1.1)
Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 16-22 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
(Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Ch.1: CAP10 to CAP13 pin inputs (4 systems) Note: In this chapter, ‘n’ refers to a channel number, and ‘m’ refers to an input/output pin number or a comparator/capture circuit number in a channel. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-1...
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31D41 TECHNICAL MANUAL...
Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-3...
5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 17-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-5...
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0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 17-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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0x0000 and then starts counting up to the new MAX val- In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-7...
When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 17-8 S1C31D41 TECHNICAL MANUAL...
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Count cycle = — — — — — — — — [s] (Eq. 17.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-9 (Rev. 1.1)
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CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 17.4.3.2 Compare Buffer Operations Seiko Epson Corporation 17-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-15...
Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-17...
Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-23 (Rev. 1.1)
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T16B_nCTL.ONEST bit setting (see Table 17.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2). Seiko Epson Corporation 17-24 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-25 (Rev. 1.1)
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-26 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-27...
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 17-28 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 17.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-29...
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T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 17-30 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 17-31 (Rev. 1.1)
(Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Function REMO O (L) IR remote controller transmit data output CLPLS O (L) IR remote controller clear pulse output * Indicates the status when the pin is configured for the REMC3. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-1 (Rev. 1.1)
1. Write 1 to the REMC3DBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 18-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 18.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-3 (Rev.
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The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC3DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMC3A- PLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bits. Figure 18.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 18-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
(REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. 18.4.4 Continuous Data Transmission and Compare Buffers Figure 18.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-5 (Rev. 1.1)
The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 18-6 S1C31D41 TECHNICAL MANUAL...
This bit sets whether the REMC3 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-7 (Rev. 1.1)
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 18-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
0x0000 H0/S0 Cleared by writing 1 to the REMC3DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-9 (Rev. 1.1)
Transfer to the REMC3APLEN buffer has not completed. 0 (R): Transfer to the REMC3APLEN buffer has completed. While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 18-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
REMC3CARR.CRPER[7:0] bit-setting value. (See Figure 18.4.3.2.) REMC3 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC3CCTL 15–9 – 0x00 – – OUTINVEN 7–1 – 0x00 – CARREN Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 18-11 (Rev. 1.1)
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This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 18-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
Figure 19.1.1 ADC12A Configuration Note: In this chapter, n, m, and k refer to an ADC12A channel number, an analog input pin number, and a 16-bit timer channel number, respectively. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-1 (Rev. 1.1)
Writing 1 to the ADC12A_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D con- version is started when an underflow occurs in the 16-bit timer Ch.k. Software trigger Writing 1 to the ADC12A_nCTL.ADST bit starts A/D conversion. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-3 (Rev. 1.1)
3. Read the A/D conversion result of the analog input m (ADC12A_nADD.ADD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12A_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 19-4 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-5...
After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 19-6 S1C31D41 TECHNICAL MANUAL...
Note: The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_ k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-7 (Rev.
A/D conversion. • Be aware that ADC circuit current I flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-9 (Rev. 1.1)
0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: ADC12A_nINTE.OVIE bit: A/D conversion result overwrite error interrupt ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 19-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 19-11 (Rev. 1.1)
If the port is shared with the TSRVR pin and other functions, the TSRVR output function must be assigned to the port before activating the TSRVR. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 20-1 (Rev.
ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 20-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
TSRVR_nVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVR_nVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external voltage to the VREFAm pin. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 20-3 (Rev. 1.1)
(Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-3 (Rev. 1.1)
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 21-4 S1C31D41 TECHNICAL MANUAL...
The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-5...
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Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 21.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 21-6 S1C31D41 TECHNICAL MANUAL...
The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more infor- mation on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-7...
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 21-8 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 21-9 (Rev. 1.1)
Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 21-10 S1C31D41 TECHNICAL MANUAL...
The fea- tures of the HWP are listed below. Sound Play function • EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format) - Sampling Frequency: 15.625 kHz - Bitrate: 16/24 kbps •...
SDAC2 positive sound signal 2 output (dedicated for four-pin output mode) SDACOUT_N2 O O (L) SDAC2 negative sound signal 2 output (dedicated for four-pin output mode) * Indicates the status when the pin is configured for SDAC2. Seiko Epson Corporation 22-2 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
The SYSCLK supply to the SDAC2 during DEBUG mode can be controlled using the SDAC2CLK.DBRUN bit. The SDAC2CLK.DBRUN bit must be set to 1 when using the Sound Play function during DEBUG mode. Be aware that the sound cannot be output normally when SDAC2CLK.DBRUN bit = 0. Seiko Epson Corporation 22-4 S1C31D41 TECHNICAL MANUAL...
- INTMASK.TO_IDLE bit (Set idle state interrupt mask) - ROMADDR.ADDRESS[31:0] bits (Set sound ROM data start address) - ROMSIZE.SIZE[31:0] bits (Set sound ROM data size) - KEYCODE.KEYCODE[31:0] bits (Set key code) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-5 (Rev. 1.1)
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This is a standby state in which the Sound Play function stops playback output. This state allows issuance of the Sound Start command. After the Sound Start command is issued, the HWP transits to sp_state_play state to start playback output. Seiko Epson Corporation 22-6 S1C31D41 TECHNICAL MANUAL...
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Single channel playback output start procedure The following shows a Ch.n playback output start procedure: 1. Confirm that the STATE_n.STATE[15:0] bits = 0x0001 (sp_state_idle). 2. Confirm that the STATUS.READY bit = 1. (Command acceptable) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-7 (Rev. 1.1)
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(fade-out) process for the playback output signal is carried out to suppress the occurrence of noise. Sound level Smoothing process Time Command execution (Mute/Pause/Stop Immediately command) Figure 22.4.1.2 Smoothing Process when Playback Output is Suspended Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-9 (Rev. 1.1)
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7. Write 0 to the HWPINTF.HWP0IF bit. (Clear interrupt flag) * Two pause commands are available. Setting the COMMAND_n.COMMAND[7:0] bits to 0x04 selects the Pause Immediately command; setting to 0x05 selects the Pause after Current Phrase command. Seiko Epson Corporation 22-10 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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(See Figure 22.4.1.3.) In the pause or mute state, the playback is terminated by releasing the pause or mute state immediately re- gardless of which of the Sound Stop commands is issued. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-11 (Rev. 1.1)
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3. Set the SDAC2CTL.TONEON bit to 1. (Start tone signal (square wave) output) Output is in progress. Terminating output 4. Set the SDAC2CTL.TONEON bit to 0. (Stop tone signal (square wave) output) Seiko Epson Corporation 22-12 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
_ram_rw _ram_march_c _checksum _crc Figure 22.4.2.1 Memory check State Transition Diagram As shown in the figure above, there are seven operating states in the Memory Check function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-13 (Rev. 1.1)
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2. Confirm that the STATUS.READY bit = 1. (Command acceptable) 3. Set the COMMAND.COMMAND[7:0] bits. (Select command) 4. Set the MEMADDR.ADDRESS[31:0] bits. (Specify check start address) 5. Set the MEMSIZE.SIZE[31:0] bits. (Specify check size (byte)) Seiko Epson Corporation 22-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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When this command is issued by the trigger bit, the HWP transits to mc_state_ram_march_c state to ex- ecute the RAM marching test (March-C algorithm). Note: When an error occurs during RAM check, the check is terminated at the address where the error has occurred. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-15 (Rev. 1.1)
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Note: The HWP uses memory mapped access mode (refer to the “Quad Synchronous Serial Interface” chapter) for the external QSPI-Flash check. Therefore, external Flash memories that do not sup- port XIP (eXecute-In-Place) cannot be checked. Seiko Epson Corporation 22-16 S1C31D41 TECHNICAL MANUAL...
1. Before disabling the HWP, set the mode byte for terminating the XIP session to the QSPI_nMB.XI- PEXT[7:0] bits. 2. Disable the HWP. 3. Perform the procedure described in Section 15.5.7. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-17 (Rev. 1.1)
STATUS Operating Status Register STATUS Operating Status Register Base + 0x48 – – RESULT Calculation Result Register Base + 0x4c VERSION Version Number Register VERSION Version Number Register Base = 0x00156700 Seiko Epson Corporation 22-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
These bits specify the sound data ROM start address. The address should be specified with a value shown below. In case of internal Flash: 0x00 0000, …, 0x02 fff0 (16-byte alignment) Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-19 (Rev. 1.1)
0x00 Silent Ch.n Repeat Control Register Register name Bit name Initial Reset Remarks REPEAT_n 15–0 REPEAT[15:0] – – (Sound Play) Bits 15–0 REPEAT[15:0] These bits specify the number of repeat playbacks. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-21 (Rev. 1.1)
Ch.n State Monitor Register Register name Bit name Initial Reset Remarks STATE_n 15–0 STATE[15:0] – – (Sound Play) Bits 15–0 STATE[15:0] These bits indicate the current state of the Sound Play function. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-23 (Rev. 1.1)
– TONEON – – RESAMPEN SDACEN Bits 15–4 Reserved Bit 3 TONEON This bit enables the square-wave tone generator. 1 (R/W): Turn on square-wave tone 0 (R/W): Turn off square-wave tone Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-29 (Rev. 1.1)
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation is enabled (HWPCTL.HWPEN bit = 1). SDAC2 Resampler Rate Register Register name Bit name Initial Reset Remarks SDAC2RESAMP 15–11 – 0x00 – – 10–0 RESAMPRATE[10:0] 0x400 Bits 15–11 Reserved Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 22-31 (Rev. 1.1)
/ [(4 × TONEDIV + 4) × 2] (Eq. 22.2) SDAC2CLK where : SDAC2 operating clock frequency set using the SDAC2CLK register [Hz] SDAC2CLK TONEDIV: Value set in the SDAC2TONE.TONEDIV[15:0] bits Seiko Epson Corporation 22-32 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
*3 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 *4 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-1 (Rev. 1.1)
= 0 V, Ta = -40 to 85°C Item Symbol Condition Min. Typ. Max. Unit – Reset hold time RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-5 (Rev. 1.1)
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= 1.8 to 5.5 V, PWGACTL.REGSEL bit = 1, Typ. value = 1.8 to 5.5 V, PWGACTL.REGSEL bit = 0, Typ. value CLGIOSC.IOSCFQ[1:0] bits = 0x1 CLGIOSC.IOSCFQ[1:0] bits = 0x2 Ta [°C] Ta [°C] Seiko Epson Corporation 23-6 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC1 internal oscillation frequency-temperature characteristic Typ. value Ta [°C]...
Flash is being programmed, as it affects the Flash memory characteristics (programming count). *2 Assumed that Erasing + Programming as count of 1. The count includes programming in the factory for shipment with ROM data programmed. Seiko Epson Corporation 23-8 S1C31D41 TECHNICAL MANUAL...
Ta = 85°C, Min. value –V = 5.5 V = 3.6 V = 1.8 V = 1.8 V = 3.6 V = 5.5 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-9 (Rev. 1.1)
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*1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVD3INTF.SVDDT bit is masked during the t period and it SVDEN retains the previous value. CLK_SVD3 SVD3CTL.MODEN 0x1e 0x10 SVD3CTL.SVDC[4:0] SVD3INTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-11 (Rev. 1.1)
– – STOP condition setup time t – – – – µs SU:STO – – Bus free time – – µs * After this period, the first clock pulse is generated. Seiko Epson Corporation 23-14 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
– – µs TEMP 0x1–0x3 TSRVR_nVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVR_nTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 5.5 V, Typ. value Ta [°C] Seiko Epson Corporation 23-16 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
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= 100 kW, Ta = 25 °C, Typ. value 1,000 1,000 5.5 V 5.5 V 3.6 V 3.6 V 1.8 V 1.8 V / IC / IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [k ] [pF] Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 23-17 (Rev. 1.1)
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= 1,000 pF, Ta = 25 °C, Typ. value 3,000 = 5.5 V = 5.5 V 3.6 V 2,500 1.8 V 2,000 3.6 V 1,500 1,000 1.8 V 1,000 10,000 Ta [°C] [kHz] RFCLK Seiko Epson Corporation 23-18 S1C31D41 TECHNICAL MANUAL (Rev. 1.1)
*1: For Flash programming *2: When OSC1 crystal oscillator is selected *3: When OSC3 crystal/ceramic oscillator is selected *4: Two-pin output mode *5: Four-pin output mode ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL 24-1 (Rev. 1.1)
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Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-B-1 (Rev. 1.1)
Continuous operation mode (SVD3CTL.SVDMD[1:0] bits = 0x0) always detects the power supply voltage, therefore, it increases current consumption. Set the supply voltage detector to intermittent operation mode or turn it on only when required. Seiko Epson Corporation AP-B-2 S1C31D41 TECHNICAL MANUAL...
Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-C-1 (Rev. 1.1)
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(2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31D41 TECHNICAL MANUAL...
The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation S1C31D41 TECHNICAL MANUAL AP-D-1 (Rev. 1.1)
REVISION HISTORY Revision History Code No. Page Contents 414190500 New establishment 414190501 1.1 Features Added the following annotation to Table 1.1.1. *2 SLEEP mode refers to deep sleep mode in the Cortex ® -M0+ processor. The RAM retains data even in SLEEP mode.
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REVISION HISTORY Code No. Page Contents 414190501 16-7 16.4.3 Data Reception in Master Mode Data receiving procedure Added Step 1. (The old step numbers were carried down in order.) 1. When receiving one-byte data, write 1 to the I2CnCTL.TXNACK bit. 16-9 16.4.3 Data Reception in Master Mode Data reception using DMA...