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BCM3116KPF [MAIN ASSY (6/12) : IC1501]
• QAM Receiver
•
Block Diagram
10
A_IF ±
A/D
67,68
AGC_CTRL
55
BAUD_CTRL
47
IF_OSC
48
GEN_CTL
46
•
Pin Function (By Pin Number)
No. I/O
Pin Name
1
G GND0
2
V VDD0
3
R_ADDR[13]
4
R_ADDR[12]
5
R_ADDR[11]
I/O
6
R_ADDR[10]
7
R_ADDR[9]
8
R_ADDR[8]
9
G GND1
10
V VDD1
11
R_ADDR[7]
12
R_ADDR[6]
I/O
13
R_ADDR[5]
14
R_ADDR[4]
15
R_ADDR[3]
16
G GND2
17
V VDD2
18
R_ADDR[2]
I/O
19
R_ADDR[1]
20
R_ADDR[0]
21
P_DATA[7]
I/O
22
P_DATA[6]
23
P_DATA[5]
24
G GND3
25
V VDD3
I : Input
O : Output
I/O : Bidirectional
Tri : Tri-stateable output
IU : Input with internal pull-up
XI : Crystal input
XO : Crystal output
Nyquist
a=.12,.18
Variable
Rate
Demod.
Nyquist
a=.12,.18
Acquisition / Tracking Loops
and Clock Generation
51
52
XTALI
XTALO
/FS4
No. I/O
Pin Name
26
P_DATA[4]
27
P_DATA[3]
I/O
28
P_DATA[2]
29
P_DATA[1]
30
O P_DATA[0]/S_OUT
31
G GND4
32
V VDD4
33
PS_VALID
34
PS_SYNC
I/O
35
PS_ERR
36
PS_CLK
37
G GND5
38
V VDD5
39 I/O SDA/MOSI
40
I
SCL/SCK
41 I/O ADDR[1]/MISO
42
I
ADDR[0]/SS
43
O BCLK
44
G GND6
45
V VDD6
46
O GEN_CTL
47
O BAUD_CTL
48
O IF_OSC
49 XO XTALO2
50
XI XTALI2
OD : Open drain output
2
Phase
Recovery
24-tap
and
DFE
8-tap
FFE
2
cos ωη
sin ωη
Phase
ROM
Tuner
JTAG
Control
73-76
79-84
JTAG[3:0]
RF[7:0]
No. I/O
Pin Name
51
XI XTALI/FS4
52 XO XTALO
53
G GND7
54
V VDD7
55
O AGC/CTL
56 I/O ADCLK
57
G GND8
58
V VDD8
59 OD IRQ
60
I
RESET
61
I
TS
62
I
SPI_I2C
63
G AGND0 (PLL)
64
V AVDD0 (PLL)
65
V AVDD1 (A/D)
66
G AGND1 (A/D)
67
A A_IF+
68
A A_IF-
69
G AGND2 (A/D)
70
V AVDD2 (A/D)
71
G AGND3 (A/D)
72
V AVDD3 (A/D)
73
ID TCK
74
IU TMS
75
IU TDI
A : Analog
ID : Input with internal pull-down
BD-V1100, BD-V1110
21-23,
P_DATA [7:0]
26-30
4
36
PS_CLK
ITU-T
J.83
34
PS_SYNC
Annex B
FEC
33
PS_VALID
Decoder
4
35
PS_ERR
3-8,11-15,
Q
18-20,87,
RAM_CTRL
88,90-92,
Deinterleaver
95-99
RAM
M-Bus/SPI
39-42,
MICRO
Interface
62
[3:0]
No. I/O
Pin Name
76
Tri TDO
77
G GND9
78
V VDD9
79
O RF_DATA[7]
80
RF_CS[0]
O
81
RF_CS[1]
82
O RF_AGC_SEL
83
O RF_BYP
84
O RF_CLK
85
G GND10
86
V VDD10
87
Tri R_WE
88
Tri R_OE
89
V VIPLVL
90
R_DATA[6]
I/O
91
R_DATA[5]
92
R_DATA[4]
93
G GND11
94
V VDD11
95
R_DATA[3]
96
R_DATA[2]
I/O
97
R_DATA[1]
98
R_DATA[0]
99 I/O R_ADDR[14]
100
I
TBYP
55
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