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1 Overview
1.1 Features
The S1C31D50/D51 is a 32-bit Arm
HW Processor. The HW Processor can perform 2-channel Voice/Audio playback, Voice Speed Conversion, and
Self Memory Check without using any CPU resource. With the HW Processor, a low memory footprint and multi-
language support are achievable because of its integrated high-compression algorithm for voice and audio. The
S1C31D50/D51 is suitable for home electronics, white goods, and battery-based products, which require a voice
and audio playback function. Furthermore, the S1C31D51 can realize a voice and audio playback function with a
buzzer and a small number of external components without using an external audio amplifier.
S1C31D50/D51 lineup
CPU
CPU core
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAMs
General-purpose RAM
Voice RAM
Instruction cache
HW processor (HWP)
Sound play function
Sound algorithm
Playback channels
Sampling frequency
Bitrate
Voice speed conversion
Sound output
Memory check function
Embedded RAM check
Embedded Flash check
External QSPI-Flash check
Sound DAC (SDAC)
Sampling frequency
Serial interfaces
UART (UART3)
Synchronous serial interface (SPIA)
Quad synchronous serial interface
(QSPI)
I
C (I2C)
2
DMA controller (DMAC)
Number of channels
Data transfer path
Transfer mode
DMA trigger source
Clock generator (CLG)
System clock source
System clock frequency
(operating frequency)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
®
Cortex
®
-M0+ MCU, which integrates a specific hardware block called the
Table 1.1.1 Features
48-pin package
64-pin package
Arm
32-bit RISC CPU core Cortex
®
Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
192K bytes (for both instructions and data)
1,000 times (min.) * When being programmed by the dedicated flash loader
On-board programming function
Flash programming voltage can be generated internally.
S1C31D50: 8K bytes
S1C31D51: 10K bytes
S1C31D50: 14K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
S1C31D51: 12K bytes (Usable as a general-purpose RAM when the HW processor is inactive.)
512 bytes
EPSON high quality and high compression algorithm (EOV: EPSON Original Sound Format)
2 channels with mixing supported (e.g. Ch.0: voice, Ch.1: BGM)
15.625 kHz
16/24/32/40 kbps
75% to 125% (5% steps)
Speaker output (S1C31D50/D51) and buzzer output (S1C31D51)
Read/write check, March-C
Checksum, CRC
Checksum, CRC
15.625 kHz
3 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
3 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
1 channel
Supports single, dual, and quad transfer modes.
Low CPU overhead memory mapped access mode that can directly read data from the exter-
nal flash memory with XIP (eXecute-In-Place) mode.
3 channels
Baud-rate generator included
4 channels
Memory to memory, memory to peripheral, and peripheral to memory
Basic, ping-pong, scatter-gather
UART3, SPIA, QSPI, I2C, T16B, ADC12A, and software
4 sources (IOSC/OSC1/OSC3/EXOSC)
V
voltage mode = mode0: 16 MHz (max.)
D1
V
voltage mode = mode1: 1.8 MHz (max.)
D1
Seiko Epson Corporation
80-pin package
-M0+
®
1 OVERVIEW
100-pin package
1-1
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