LG CED-8042B Manual page 23

Monitor Register (0X3E)
The source of Monitor 0 is set by setting registers. as bellow.
Monitor 0 Sel (bit-0) [R/W]
bit3..0 Monitor 0
0 Reserved
1 BSYNC
2 PROTECT
3 READSTART
4 IDSFS
5 ACRCOK
6 FGLOCK
7 WBLOCK
8 REFE
9 VIRT
A FSCK
B AXREF
C DREQ
D COD
E BSY
F I/O
Power Supply
Pin No.
33, 45, 62, 76, 86, 96,
106, 117, 132, 165
10, 50, 90, 141, 144
145
148
7, 11, 28, 38, 51, 57, 68,
71, 81, 91, 101, 112, 122,
127, 143, 149, 161, 175
46
Description
Reserved
BSYNC
PROTECT
READSTART
Internal Subcode Frame Sync : Sync after operation of insertion
ACRCOK
FG servo lock
WBL servo lock
PLL phase comparator reference output
PLL phase comparator virtual output
FSCK
AX servo reference output
ATAPI DREQ
ATAPI COD
ATAPI BSY
ATAPI I/O
Pin Name Description
DVCC5V 5V VCC : +5V Pin. Connect to digital +5V
DVCC3V 3V VCC : +3.3V Pin. Connect to digital +3.3V
AVCC3V 3V VCC : +3.3V Pin. Connect to analong +3.3V for PLL
AGND GND Pin : Connect to analong GND for PLL
DGND GND Pin : Connect to digital GND