LG CED-8042B Manual page 17

Pin No. Symbol
123 TES2 I
124 TES3 I
129 PWMI I
130 DV 5 I
DD
131 VCOO O
132 VCOI I
133 TEST I
134 PDO O
135 VCKI I
136 V16M O
137 AV 2
DD
138 IGEN I
139 AV 2
SS
140 ADIO O
141 RFDC I
142 CE I
143 TE I
Notes :
• The data at the 64-bit slot is output in 2's complements on an LSB-first basis.
The data at the 48-bit slot is output in 2's complements on an MSB-first basis.
• GTOP monitors the state of Frame Sync protection. ("H" : Sync protection window released)
• XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected.
• XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
coincides with a change point of the EFM signal.
• The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.
• RFCK is a signal generated at 136-•Ï s periods using a crystal oscillator.
• C2PO is a signal to indicate data error.
• XRAOF is a signal issued when a jitter margin of °æ28F is exceeded by the 32K RAM.
40
I/O
Test Pin. Normally "L"
Test Pin. Normally "L"
External input of spindle motor
Digital power supply
1, 0 Output of oscillation circuit analog EFM PLL
Input to oscillation circuit for analog EFM PLL. f
Test Pin. Normally "L"
1, Z, 0 Output of charge pump for analog EFM PLL
Clock input from external VCO for vari-pitch control. fc
1, Z, 0 Output of VC02 oscillation for vari-pitch EFM PLL
Analog power supply
Resistor connection pin of current source reference for OP Amp
Analog GND
OP Amp output
RF signal input
Center servo analog input
Tracking error signal input
Description
=8.6436MHz
LOCK
=16.9344MHz
center