Lattice Semiconductor ispClock5620A Application Note

Interfacing ispClock5600A with
Reference Clock Oscillators
August 2008 Application Note AN6079
Introduction
Lattice ispClock™5620A and ispClock5610A are in-system programmable zero delay clock generator ICs with inte-
grated universal fan-out buffers. In some applications these devices are required to generate multiple clock output
frequencies from a single reference oscillator clock source.
The input to output clock phase relation is guaranteed only when the reference clock high pulse width or low pulse
width are greater than the data sheet t and t specifications. If either specification is violated the
CLOCKHI CLOCKLOW
input to output clock phase relationship can be restored by activation of the RESET pin of the ispClock 5600A
device. This application note examines two common conditions when the reference oscillator clock could violate
the t or t specifications and warrant the activation of the RESET pin.
CLOCKHI CLOCKLOW
Powering Up Reference Oscillator After ispClock5600A
Figure 1 details the start-up behavior of a typical oscillator module. Note that for the first 50ms the output is active,
the amplitude and offset are ramping up. It is during this time that the ispClock may see a very narrow clock pulse
because the thresholds at the ispClock inputs are fixed but the oscillator output is changing. In this case the
RESET pin of the ispClock should be activated after the oscillator output is stable.
Figure 1. Powering Up a Reference Oscillator
Oscillator Enabled Asynchronously
Figure 2 shows the general behavior of a typical oscillator module when the output enable pin is controlled by an
asynchronous enable signal. The output is held low when the enable pin is low and oscillates when the enable pin
goes high. Figure 3 zooms in on the initial output transitions and reveals two short pulses that would result in a tim-
ing violation for the reference clock input of the ispClock.
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