Texas Instruments TMS320C2XX Manuals

Manuals and User Guides for Texas Instruments TMS320C2XX. We have 2 Texas Instruments TMS320C2XX manuals available for free PDF download: User Manual

Texas Instruments TMS320C2XX User Manual (587 pages)

Digital signal processors (DSPs)

Brand: Texas Instruments | Category: Processor | Size: 3.31 MB

Table of Contents

12
Chapter 4 Memory and I\/O Spaces

63
- Overview of the Memory and I/O Spaces
  64
- Pins for Interfacing to External Memory and I/O Spaces
  65
- Pins for Interfacing with External Memory and I/O Spaces
  65
  - Signals
    66
- Interfacing with External Program Memory
  67
- Obtain the Proper Timing Information
  67
- Program Memory
  67
- Interface with External Program Memory
  68
- Local Data Memory
  69
- Pages of Data Memory
  69
- Data Page 0 Address Map
  70
- Do Not Write to Test/Emulation Addresses
  70
- Interfacing with External Local Data Memory
  71
- Obtain the Proper Timing Information
  71
- Interface with External Local Data Memory
  72
- Global Data Memory Configurations
  73
- Global and Local Data Memory for GREG = 11100000
  74
- Global Data Memory
  74
- GREG Register Set to Configure 8K for Global Data Memory
  74
- Interfacing with External Global Data Memory
  74
- Using 8000H-Ffffh for Local and Global External Memory
  75
- Boot Loader
  76
- Choosing an EPROM
  76
- Simplified Block Diagram of Boot Loader Operation
  76
- Connecting the EPROM to the Processor
  77
- Programming the EPROM
  78
- Enabling the Boot Loader
  79
- Storing the Program in the EPROM
  79
- Boot Loader Execution
  80
- Program Code Transferred from 8-Bit EPROM to 16-Bit RAM
  81
- Interrupt Vectors Transferred First During Boot Load
  82
- Boot Loader Program
  83
- I/O Address Map for the 'C2Xx
  85
- I/O Space
  85
- Do Not Write to Reserved Addresses
  86
- On-Chip Registers Mapped to I/O Space
  86
- Accessing I/O Space
  87
- I/O Port Interface Circuitry
  88
- Direct Memory Access Using the HOLD Operation
  89
- An Interrupt Service Routine Supporting INT1 and HOLD
  90
- HOLD Deasserted before Reset Deasserted
  91
- HOLD During Reset
  91
- Reset Deasserted before HOLD Deasserted
  92
- Device-Specific Information
  93
- TMS320C203 Address Maps and Memory Configuration
  93
- C203 Address Map
  94
- C203 Program-Memory Configuration Options
  95
- Do Not Write to Reserved Addresses
  95
- C203 Data-Memory Configuration Options
  96
- TMS320C204 Address Maps and Memory Configuration
  96
- C204 Address Map
  97
- Do Not Write to Reserved Addresses
  98
- C204 Data-Memory Configuration Options
  99
- C204 Program-Memory Configuration Options
  99
- Program Control
  100
- Program-Address Generation Block Diagram
  101
  - Program Counter (PC)
    102
- Program-Address Generation Summary
  102
  - Interrupts
    103
  - Stack
    103
- Address Loading to the Program Counter
  103
- A Push Operation
  104
  - Micro Stack (MSTACK)
    105
- A Pop Operation
  105
- Branches, Calls, and Returns
  107
  - Unconditional Branches
    107
  - Unconditional Calls
    107
  - Unconditional Returns
    108
  - Conditional Branches, Calls, and Returns
    109
  - Using Multiple Conditions
    109
- Conditions for Conditional Calls and Returns
  109
  - Stabilization of Conditions
    110
- Conditional Branches
  110
- Groupings of Conditions
  110
  - Conditional Calls
    111
  - Conditional Returns
    111
- Repeating a Single Instruction
  113
  - Interrupt Operation: Three Phases
    114
    
    Interrupts
    114
    
    Interrupt Table
    115
- C2Xx Interrupt Locations and Priorities
  115
  - Maskable Interrupts
    117
- INT2/INT3 Request Flow Chart
  117
  - Interrupt Flag Register (IFR)
    119
- Maskable Interrupt Operation Flow Chart
  119
- C2Xx Interrupt Flag Register (IFR) - Data-Memory Address 0006H
  120
  - Interrupt Mask Register (IMR)
    121
- C2Xx Interrupt Mask Register (IMR) - Data-Memory Address 0004H
  122
  - Interrupt Control Register (ICR)
    123
- C2Xx Interrupt Control Register (ICR) - I/O-Space Address Ffech
  125
  - Nonmaskable Interrupts
    126
  - Interrupt Service Routines (Isrs)
    128
- Nonmaskable Interrupt Operation Flow Chart
  128
  - Interrupt Latency
    129
- Reset Operation
  132
- Reset Values of On-Chip Registers Mapped to Data Space
  134
- Reset Values of On-Chip Registers Mapped to I/O Space
  134
- Power-Down Mode
  135
  - Normal Termination of Power-Down Mode
    135
  - Termination of Power-Down During a HOLD Operation
    136
- Addressing Modes
  137
- Assembly Language Instructions
  154
  - Instruction Set Summary
    155
  - Accumulator, Arithmetic, and Logic Instructions
    157
  - Auxiliary Register Instructions
    160
  - TREG, PREG, and Multiply Instructions
    160
  - Branch Instructions
    161
  - Control Instructions
    162
  - I/O and Memory Instructions
    163
  - How to Use the Instruction Descriptions
    165
    
    Syntax
    165
    
    Opcode
    167
    
    Operands
    167
    
    Description
    168
    
    Execution
    168
    
    Status Bits
    168
    
    Cycles
    169
    
    Words
    169
  - Examples
    171
  - Instruction Descriptions
    173
  - Product Shift Modes
    190
  - Bit Numbers and Their Corresponding Bit Codes for BIT Instruction
    198
  - Bit Numbers and Their Corresponding Bit Codes for BITT Instruction
    200
  - LST #0 Operation
    240
  - LST #1 Operation
    241
  - Product Shift Modes
    320
Chapter 8 On-Chip Peripherals

351
- Control of On-Chip Peripherals
  352
- For Examples of Program Code for the On-Chip Peripherals, See Appendix C
  352
- Peripheral Register Locations and Reset Conditions
  352
- Clock Generator
  354
  - Clock Generator Options
    355
- Using the Internal Oscillator
  354
- Using an External Oscillator
  355
- C2Xx Input Clock Modes
  356
- C2Xx CLK Register - I/O-Space Address Ffe8H
  357
- CLKOUT1-Pin Control (CLK) Register
  357
- Timer
  358
  - Timer Operation
    359
  - Timer Control Register (TCR)
    360
- Timer Functional Block Diagram
  358
- C2Xx Timer Control Register (TCR) - I/O-Space Address Fff8H
  361
- C2Xx Timer Run/Emulation Modes
  361
- Wait-State Generator
  364
  - Generating Wait States with the READY Signal
    364
  - Generating Wait States with the 'C2Xx Wait-State Generator
    364
- C2Xx Wait-State Generator Control Register (WSGR)
  365
  - I/O-Space Address Fffch
    365
- Setting the Number of Wait States with the 'C2Xx WSGR Bits
  366
- General-Purpose I/O Pins
  367
  - Input Pin BIO
    367
  - Output Pin XF
    368
  - Input/Output Pins IO0, IO1, IO2, and IO3
    368
- BIO Timing Diagram Example
  368
Chapter 9 Synchronous Serial Port

369
Appendix Eappendix a Design Considerations for Using Xds510 Emulator

513

Texas Instruments TMS320C2XX User Manual (250 pages)

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Texas Instruments TMS320C2XX Manuals

Texas Instruments TMS320C2XX User Manual (587 pages)

Table of Contents

Table of Contents

Chapter 4 Memory and I\/O Spaces

Chapter 8 On-Chip Peripherals

Chapter 9 Synchronous Serial Port

Appendix Eappendix a Design Considerations for Using Xds510 Emulator

Appendix A

Appendix E

Texas Instruments TMS320C2XX User Manual (250 pages)

Table of Contents

Table of Contents

Chapter 3 Optimizing Your Code

Chapter 6 Run-Time Environment

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