Texas Instruments MSP430FR57 Series Manuals

Texas Instruments MSP430FR57 Series Manuals

Manuals and User Guides for Texas Instruments MSP430FR57 Series. We have 1 Texas Instruments MSP430FR57 Series manual available for free PDF download: User Manual

Texas Instruments MSP430FR57 Series User Manual

Texas Instruments MSP430FR57 Series User Manual (578 pages)

Brand: Texas Instruments | Category: Motherboard | Size: 3.39 MB

Table of Contents

Msp430Fr57Xx Family User's Guide

2
- Table of Contents
  2
10
- Preface
  
  24
- 1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
  
  26
  - Connection of Unused Pins
    26
  - SFR Registers
    26
  - SYS Registers
    26
  - System Control Module (SYS) Introduction
    27
  - System Reset and Initialization
    27
  - BOR, POR, and PUC Reset Circuit
    28
    
    Device Initial Conditions after System Reset
    29
    
    Interrupt Priority
    29
    
    Interrupts
    29
    
    Maskable Interrupts
    30
    
    Non)Maskable Interrupts (Nmis)
    30
    
    SNMI Timing
    30
    
    Interrupt Processing
    31
    
    Interrupt Nesting
    32
    
    Interrupt Sources, Flags, and Vectors
    32
    
    Interrupt Vectors
    32
    
    Return from Interrupt
    32
    
    SYS Interrupt Vector Generators
    33
    
    Operating Modes
    35
  - Operation Modes
    36
    
    Low-Power Modes and Clock Requests
    37
    
    Operation Modes
    37
    
    Requested Vs Actual LPM
    37
    
    Entering and Exiting Low-Power Modes LPM0 through LPM4
    38
    
    Entering and Exiting Low-Power Modes Lpmx.5
    38
    
    Principles for Low-Power Applications
    39
    
    Configuring JTAG Pins
    40
    
    Connection of Unused Pins
    40
    
    Reset Pin (RST/NMI) Configuration
    40
    
    Boot Code
    41
    
    Bootstrap Loader (BSL)
    41
    
    JTAG Mailbox (JMB) System
    41
    
    Vacant Memory Space
    41
    
    JMB Configuration
    42
    
    JMB NMI Usage
    42
    
    JMBIN0 and JMBIN1 Incoming Mailbox
    42
    
    JMBOUT0 and JMBOUT1 Outgoing Mailbox
    42
    
    JTAG and SBW Lock Mechanism Using the Electronic Fuse
    42
    
    Device Descriptor Table
    43
    
    JTAG and SBW Lock with Password
    43
    
    JTAG and SBW Lock Without Password
    43
    
    Devices Descriptor Table
    44
    
    Identifying Device Type
    44
    
    Tag Values
    45
    
    TLV Descriptors
    45
    
    Calibration Values
    46
    
    REF Calibration Tags
    46
  - ADC Calibration Tags
    47
  - BSL Configuration Tags
    48
    
    BSL_CIF_CONFIG Values
    49
    
    SFR Registers
    49
    
    SFRIE1 Register
    50
    
    SFRIE1 Register Description
    50
    
    SFRIFG1 Register
    51
    
    SFRIFG1 Register Description
    51
    
    SFRRPCR Register
    53
    
    SFRRPCR Register Description
    53
    
    SYS Registers
    54
    
    SYSCTL Register
    55
    
    SYSCTL Register Description
    55
    
    SYSJMBC Register
    56
    
    SYSJMBC Register Description
    56
    
    SYSJMBI0 Register
    57
    
    SYSJMBI0 Register Description
    57
    
    SYSJMBI1 Register
    57
    
    SYSJMBI1 Register Description
    57
    
    SYSJMBO0 Register
    58
    
    SYSJMBO0 Register Description
    58
    
    SYSJMBO1 Register
    58
    
    SYSJMBO1 Register Description
    58
    
    SYSSNIV Register
    59
    
    SYSSNIV Register Description
    59
    
    SYSUNIV Register
    59
    
    SYSUNIV Register Description
    59
    
    SYSRSTIV Register
    60
    
    SYSRSTIV Register Description
    60
- 2 Power Management Module and Supply Voltage Supervisor
  
  61
  - Power Management Module (PMM) Introduction
    62
  - PMM Block Diagram
    62
  - PMM Operation
    63
    
    Supply Voltage Supervisor
    63
    
    VCORE and the Regulator
    63
  - High-Side and Low-Side Voltage Failure and Resulting PMM Actions
    63
    
    Brownout Reset (BOR)
    64
    
    Lpm3.5, Lpm4.5
    64
    
    Rst/Nmi
    64
    
    Supply Voltage Supervisor - Power-Up
    64
  - PMM Action at Device Power-Up
    64
    
    PMM Interrupts
    65
    
    Port I/O Control
    65
  - PMM Registers
    66
    
    PMMCTL0 Register
    67
  - PMMCTL0 Register Description
    67
    
    PMMIFG Register
    68
  - PMMIFG Register Description
    68
    
    PM5CTL0 Register
    69
  - PM5CTL0 Register Description
    69
- 3 Clock System (CS)
  
  70
  - Clock System Introduction
    71
  - Clock System Block Diagram
    72
    
    Clock System Operation
    73
    
    CS Module Features for Low-Power Applications
    73
    
    Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    73
    
    XT1 Oscillator
    73
    
    Digitally Controlled Oscillator (DCO)
    74
    
    XT2 Oscillator
    74
    
    Module Request Clock System
    75
    
    Operation from Low-Power Modes, Requested by Peripheral Modules
    75
    
    CS Module Fail-Safe Operation
    76
    
    System Clocks Vs Power Modes and Clock Requests
    76
  - Oscillator Fault Logic
    77
    
    MODOSC Operation
    78
    
    Module Oscillator (MODOSC)
    78
    
    Switch MCLK from DCOCLK to XT1CLK
    78
    
    Synchronization of Clock Signals
    78
    
    CS Registers
    79
    
    CSCTL0 Register
    80
    
    CSCTL0 Register Description
    80
    
    CSCTL1 Register
    81
    
    CSCTL1 Register Description
    81
    
    CSCTL2 Register
    82
    
    CSCTL2 Register Description
    82
    
    CSCTL3 Register
    83
    
    CSCTL3 Register Description
    83
    
    CSCTL4 Register
    84
    
    CSCTL4 Register Description
    84
    
    CSCTL5 Register
    85
    
    CSCTL5 Register Description
    85
    
    CSCTL6 Register
    86
    
    CSCTL6 Register Description
    86
- 4 Cpux
  
  87
  - MSP430X CPU (CPUX) Introduction
    88
  - MSP430X CPU Block Diagram
    89
    
    Interrupts
    90
    
    PC Storage on the Stack for Interrupts
    90
    
    CPU Registers
    91
    
    PC Storage on the Stack for CALLA
    91
    
    Program Counter
    91
    
    Program Counter (PC)
    91
    
    Stack Pointer (SP)
    91
  - Stack Pointer
    92
  - Stack Usage
    92
  - PUSHX.A Format on the Stack
    92
  - PUSH SP, POP SP Sequence
    92
    
    SR Bit Description
    93
    
    SR Bits
    93
    
    Status Register (SR)
    93
    
    Constant Generator Registers (CG1 and CG2)
    94
    
    Values of Constant Generators CG1, CG2
    94
    
    General-Purpose Registers (R4 to R15)
    95
    
    Register-Byte and Byte-Register Operation
    95
    
    Register-Word Operation
    95
  - Word-Register Operation
    96
  - Register - Address-Word Operation
    96
    
    Address-Word - Register Operation
    97
    
    Addressing Modes
    97
    
    Source and Destination Addressing
    97
    
    Register Mode
    98
    
    Indexed Mode
    99
    
    Indexed Mode in Lower 64 KB
    99
  - Indexed Mode in Upper Memory
    100
  - Overflow and Underflow for Indexed Mode
    101
  - Example for Indexed Mode
    102
    
    Symbolic Mode
    103
  - Symbolic Mode Running in Lower 64 KB
    104
  - Symbolic Mode Running in Upper Memory
    105
  - Overflow and Underflow for Symbolic Mode
    106
    
    Absolute Mode
    108
    
    Indirect Register Mode
    110
    
    Indirect Autoincrement Mode
    111
    
    Immediate Mode
    112
    
    MSP430 and MSP430X Instructions
    114
    
    MSP430 Double-Operand Instruction Format
    114
    
    MSP430 Instructions
    114
  - MSP430 Single-Operand Instructions
    115
  - MSP430 Double-Operand Instructions
    115
  - Format of Conditional Jump Instructions
    116
  - Conditional Jump Instructions
    116
  - Emulated Instructions
    116
  - Interrupt, Return, and Reset Cycles and Length
    117
  - MSP430 Format II Instruction Cycles and Length
    117
  - MSP430 Format I Instructions Cycles and Length
    118
    
    Description of the Extension Word Bits for Register Mode
    119
    
    Extension Word for Non-Register Modes
    119
    
    Extension Word for Register Modes
    119
    
    MSP430X Extended Instructions
    119
  - Example for Extended Register or Register Instruction
    120
  - Description of Extension Word Bits for Non-Register Modes
    120
  - Example for Extended Immediate or Indexed Instruction
    121
  - Extended Double-Operand Instructions
    121
  - Extended Format I Instruction Formats
    122
  - Extended Format II Instruction Format
    123
  - Extended Single-Operand Instructions
    123
  - PUSHM and POPM Instruction Format
    124
  - RRCM, RRAM, RRUM, and RLAM Instruction Format
    124
  - BRA Instruction Format
    124
  - CALLA Instruction Format
    124
  - Extended Emulated Instructions
    125
  - Address Instructions, Operate on 20-Bit Register Data
    126
  - MSP430X Format II Instruction Cycles and Length
    127
  - MSP430X Format I Instruction Cycles and Length
    128
  - Address Instruction Cycles and Length
    129
    
    Instruction Map of MSP430X
    130
    
    Instruction Set Description
    130
    
    Extended Instruction Binary Descriptions
    131
    
    MSP430 Instructions
    133
  - Decrement Overlap
    150
  - Stack after a RET Instruction
    169
  - Destination Operand-Arithmetic Shift Left
    171
  - Destination Operand-Carry Left Shift
    172
  - Rotate Right Arithmetically RRA.B and RRA.W
    173
  - Rotate Right through Carry RRC.B and RRC.W
    174
  - Swap Bytes in Memory
    181
  - Swap Bytes in a Register
    181
    
    Extended Instructions
    185
  - Rotate Left Arithmetically-RLAM[.W] and RLAM.A
    208
  - Destination Operand-Arithmetic Shift Left
    209
  - Destination Operand-Carry Left Shift
    210
  - Rotate Right Arithmetically RRAM[.W] and RRAM.A
    211
  - Rotate Right Arithmetically RRAX(.B,.A) - Register Mode
    213
  - Rotate Right Arithmetically RRAX(.B,.A) - Non-Register Mode
    213
  - Rotate Right through Carry RRCM[.W] and RRCM.A
    215
  - Rotate Right through Carry RRCX(.B,.A) - Register Mode
    217
  - Rotate Right through Carry RRCX(.B,.A) - Non-Register Mode
    217
  - Rotate Right Unsigned RRUM[.W] and RRUM.A
    218
  - Rotate Right Unsigned RRUX(.B,.A) - Register Mode
    219
  - Swap Bytes SWPBX.A Register Mode
    223
  - Swap Bytes SWPBX.A in Memory
    223
  - Swap Bytes SWPBX[.W] Register Mode
    224
  - Swap Bytes SWPBX[.W] in Memory
    224
  - Sign Extend SXTX.A
    225
  - Sign Extend SXTX[.W]
    225
    
    Address Instructions
    228
- 5 FRAM Controller (FRCTL)
  
  243
  - FRAM Introduction
    244
  - FRAM Organization
    244
  - FRCTL Module Operation
    244
  - FRAM Controller Block Diagram
    244
  - Programming FRAM Memory Devices
    245
    
    Programming FRAM Memory by Bootstrap Loader (BSL)
    245
    
    Programming FRAM Memory by Custom Solution
    245
    
    Programming FRAM Memory by JTAG or Spy-Bi-Wire
    245
  - Wait State Control
    245
    
    Manual Wait State Control
    245
    
    Automatic Wait State Control
    246
    
    Safe Access
    246
    
    Wait State and Cache Hit
    246
  - Fram Ecc
    246
  - Manual Wait State Settings
    246
  - FRCTL Registers
    247
    
    FRCTL0 Register
    248
  - FRCTL0 Register Description
    248
    
    GCCTL0 Register
    249
  - GCCTL0 Register Description
    249
    
    GCCTL1 Register
    250
  - GCCTL1 Register Description
    250
- 6 Memory Protection Unit (MPU)
  
  251
  - Memory Protection Unit (MPU) Introduction
    252
  - Memory Protection Unit Overview
    252
  - MPU Segments
    253
    
    Main Memory Segments
    253
    
    Segment Border Setting
    253
  - Segmentation of Main Memory
    253
  - Page Addresses for 16KB, 8KB, and 4KB Main Memory
    254
    
    Information Memory
    255
    
    MPU Access Management Settings
    255
    
    Segment Access Rights
    255
    
    Interrupt Table and Reset Vector
    256
    
    MPU Violations
    256
    
    Violation Handling
    256
    
    MPU Registers
    257
    
    MPUCTL0 Register
    258
    
    MPUCTL0 Register Description
    258
    
    MPUCTL1 Register
    259
    
    MPUCTL1 Register Description
    259
    
    MPUSEG Register
    260
    
    MPUSEG Register Description
    260
    
    MPUSAM Register
    261
    
    MPUSAM Register Description
    261
    
    MPUIV Register
    263
    
    MPUIV Register Description
    263
- 7 DMA Controller
  
  264
  - Direct Memory Access (DMA) Introduction
    265
  - DMA Controller Block Diagram
    266
    
    DMA Addressing Modes
    267
    
    DMA Operation
    267
    
    DMA Transfer Modes
    268
  - DMA Single Transfer State Diagram
    269
  - DMA Block Transfer State Diagram
    271
  - DMA Burst-Block Transfer State Diagram
    273
  - DMA Trigger Operation
    275
  - Maximum Single-Transfer DMA Cycle Time
    276
  - DMA Registers
    279
  - DMACTL0 Register
    281
  - DMACTL0 Register Description
    281
  - DMACTL1 Register
    282
  - DMACTL1 Register Description
    282
  - DMACTL2 Register
    283
  - DMACTL2 Register Description
    283
  - DMACTL3 Register
    284
  - DMACTL3 Register Description
    284
  - DMACTL4 Register
    285
  - DMACTL4 Register Description
    285
  - Dmaxctl Register
    286
  - Dmaxctl Register Description
    286
  - Dmaxsa Register
    288
  - Dmaxsa Register Description
    288
  - Dmaxda Register
    289
  - Dmaxda Register Description
    289
  - Dmaxsz Register
    290
  - Dmaxsz Register Description
    290
  - DMAIV Register
    291
  - DMAIV Register Description
    291
  - I/O Configuration
    292
  - Digital I/O Registers
    292
  - I/O Function Selection
    295
  - P1IV Register
    313
  - P2IV Register
    313
  - P1IV Register Description
    313
  - P2IV Register Description
    313
  - P3IV Register
    314
  - P4IV Register
    314
  - P3IV Register Description
    314
  - P4IV Register Description
    314
  - Pxin Register
    315
  - Pxout Register
    315
  - Pxdir Register
    315
  - Pxin Register Description
    315
  - Pxout Register Description
    315
  - P1DIR Register Description
    315
  - Pxren Register
    316
  - Pxsel0 Register
    316
  - Pxsel1 Register
    316
  - Pxren Register Description
    316
  - Pxsel0 Register Description
    316
  - Pxsel1 Register Description
    316
  - Pxselc Register
    317
  - Pxies Register
    317
  - Pxie Register
    317
  - Pxselc Register Description
    317
  - Pxies Register Description
    317
  - Pxie Register Description
    317
  - Pxifg Register
    318
  - Pxifg Register Description
    318
  - LFSR Implementation of CRC-CCITT Standard, Bit 0 Is the MSB of the Result
    320
  - Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers
    322
  - CRC Registers
    324
  - CRCDI Register
    325
  - CRCDIRB Register
    325
  - CRCDI Register Description
    325
  - CRCDIRB Register Description
    325
  - CRCINIRES Register
    326
  - CRCRESR Register
    326
  - CRCINIRES Register Description
    326
  - CRCRESR Register Description
    326
  - Watchdog Timer Block Diagram
    329
  - WDTCTL Register
    333
  - WDTCTL Register Description
    333
  - Timer_A Registers
    334
  - Timer_A Block Diagram
    336
  - Up Mode
    338
  - Timer Modes
    338
  - Continuous Mode
    339
  - Continuous Mode Flag Setting
    339
  - Continuous Mode Time Intervals
    339
  - Up/Down Mode
    340
  - Up/Down Mode Flag Setting
    340
  - Output Unit in Up/Down Mode
    341
  - Capture Signal (SCS = 1)
    342
  - Capture Cycle
    342
  - Output Modes
    343
  - Output Example - Timer in up Mode
    344
  - Output Example - Timer in Continuous Mode
    345
  - Output Example - Timer in Up/Down Mode
    346
  - Taxctl Register
    350
  - Taxctl Register Description
    350
  - Taxr Register
    351
  - Taxr Register Description
    351
  - Taxcctln Register
    352
  - Taxcctln Register Description
    352
  - Capture/Compare Interrupt Flag
    353
  - Taxccrn Register
    354
  - Taxiv Register
    354
  - Taxccrn Register Description
    354
  - Taxiv Register Description
    354
  - Taxex0 Register
    355
  - Taxex0 Register Description
    355
  - Timer_B Registers
    356
  - Timer_B Block Diagram
    358
  - Up Mode Flag Setting
    360
  - Timer Modes
    360
  - Continuous Mode
    361
  - Continuous Mode Flag Setting
    361
  - Continuous Mode Time Intervals
    361
  - Up/Down Mode
    362
  - Up/Down Mode Flag Setting
    362
  - Output Unit in Up/Down Mode
    363
  - Capture Signal (SCS = 1)
    364
  - Capture Cycle
    364
  - Tbxcln Load Events
    365
    
    Mode
    366
  - Compare Latch Operating Modes
    366
  - Output Modes
    366
  - Output Example - Timer in up Mode
    367
  - Output Example - Timer in Continuous Mode
    368
  - Output Example - Timer in Up/Down Mode
    369
  - Capture/Compare Tbxccr0 Interrupt Flag
    370
  - Tbxctl Register
    373
  - Tbxctl Register Description
    373
  - Tbxr Register
    375
  - Tbxr Register Description
    375
  - Tbxcctln Register
    376
  - Tbxcctln Register Description
    376
  - Tbxccrn Register
    378
  - Tbxccrn Register Description
    378
  - Tbxiv Register
    379
  - Tbxiv Register Description
    379
  - Tbxex0 Register
    380
  - Tbxex0 Register Description
    380
  - RTC_B Block Diagram
    383
  - RTC_B Registers
    390
  - RTCCTL0 Register
    391
  - RTCCTL0 Register Description
    391
  - RTCCTL1 Register
    392
  - RTCCTL1 Register Description
    392
  - RTCCTL2 Register
    393
  - RTCCTL3 Register
    393
  - RTCCTL2 Register Description
    393
  - RTCCTL3 Register Description
    393
  - RTCSEC Register
    394
  - RTCSEC Register Description
    394
  - RTCMIN Register
    395
  - RTCMIN Register Description
    395
  - RTCHOUR Register
    396
  - RTCHOUR Register Description
    396
  - RTCDOW Register
    397
  - RTCDAY Register
    397
  - RTCDOW Register Description
    397
  - RTCDAY Register Description
    397
  - RTCMON Register
    398
  - RTCMON Register Description
    398
  - RTCYEAR Register
    399
  - RTCYEAR Register Description
    399
  - RTCAMIN Register
    400
  - RTCAMIN Register Description
    400
  - RTCAHOUR Register
    401
  - RTCAHOUR Register Description
    401
  - RTCADOW Register
    402
  - RTCADOW Register Description
    402
  - RTCADAY Register
    403
  - RTCADAY Register Description
    403
  - RTCPS0CTL Register
    404
  - RTCPS1CTL Register
    405
  - RTCPS0 Register
    406
  - RTCPS1 Register
    406
  - RTCPS0 Register Description
    406
  - RTCPS1 Register Description
    406
  - RTCIV Register
    407
  - RTCIV Register Description
    407
  - BIN2BCD Register
    408
  - BCD2BIN Register
    408
  - BIN2BCD Register Description
    408
  - BCD2BIN Register Description
    408
  - MPY32 Block Diagram
    411
  - Result Availability (MPYFRAC = 0, MPYSAT = 0)
    412
  - OP1 Registers
    413
  - OP2 Registers
    413
  - SUMEXT and MPYC Contents
    414
  - Q15 Format Representation
    416
  - Q14 Format Representation
    416
  - Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0)
    417
  - Saturation Flow Chart
    418
  - Result Availability in Saturation Mode (MPYSAT = 1)
    418
  - Multiplication Flow Chart
    420
  - MPY32 Registers
    424
  - Alternative Registers
    425
  - MPY32CTL0 Register
    426
  - MPY32CTL0 Register Description
    426
  - REF Block Diagram
    428
  - REF Control of Reference System (REFMSTR = 1) (Default)
    429
  - REF Registers
    431
  - REFCTL0 Register
    432
  - REFCTL0 Register Description
    432
  - ADC10_B Block Diagram
    435
  - Analog Multiplexer
    436
  - Extended Sample Mode
    438
  - Pulse Sample Mode
    438
  - Analog Input Equivalent Circuit
    439
  - Conversion Mode Summary
    439
  - Single-Channel Single-Conversion Mode
    440
  - Sequence-Of-Channels Mode
    441
  - Repeat-Single-Channel Mode
    442
  - Repeat-Sequence-Of-Channels Mode
    443
  - Typical Temperature Sensor Transfer Function
    445
  - ADC10_B Grounding and Noise Considerations
    446
  - ADC10_B Registers
    449
  - ADC10CTL0 Register
    450
  - ADC10CTL0 Register Description
    450
  - ADC10CTL1 Register
    452
  - ADC10CTL1 Register Description
    453
  - ADC10CTL2 Register
    454
  - ADC10MEM0 Register
    455
  - ADC10MEM0 Register Description
    455
  - ADC10MCTL0 Register
    456
  - ADC10MCTL0 Register Description
    456
  - ADC10HI Register
    457
  - ADC10HI Register Description
    457
  - ADC10LO Register
    458
  - ADC10LO Register Description
    458
  - ADC10IE Register
    459
  - ADC10IE Register Description
    459
  - ADC10IFG Register
    460
  - ADC10IFG Register Description
    460
  - ADC10IV Register
    461
  - ADC10IV Register Description
    461
  - Comparator_D Registers
    462
  - Comparator_D Block Diagram
    463
  - Comparator_D Sample-And-Hold
    465
  - RC-Filter Response at the Output of the Comparator
    466
  - Reference Generator Block Diagram
    466
  - Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer
    467
  - Temperature Measurement System
    467
  - Timing for Temperature Measurement Systems
    468
  - CDCTL0 Register
    470
  - CDCTL0 Register Description
    470
  - CDCTL1 Register
    471
  - CDCTL1 Register Description
    471
  - CDCTL2 Register
    472
  - CDCTL2 Register Description
    472
  - CDCTL3 Register
    473
  - CDCTL3 Register Description
    473
  - CDINT Register
    474
  - CDINT Register Description
    474
  - CDIV Register
    475
  - CDIV Register Description
    475
  - Eusci_Ax Block Diagram - UART Mode (UCSYNC = 0)
    478
  - Character Format
    479
  - Idle-Line Format
    480
  - Address-Bit Multiprocessor Format
    481
  - Auto Baud-Rate Detection - Break/Synch Sequence
    482
  - Auto Baud-Rate Detection - Synch Field
    482
  - UART Vs Irda Data Format
    483
  - Receive Error Conditions
    484
  - Glitch Suppression, Eusci_A Receive Not Started
    485
  - BITCLK Baud-Rate Timing with UCOS16
    486
  - Modulation Pattern Examples
    486
  - BITCLK16 Modulation Pattern
    487
    
    BRCLK /Baudrate
    488
  - Receive Error
    490
  - Recommended Settings for Typical Crystals and Baudrates
    491
  - UART State Change Interrupt Flags
    493
    
    State Change Interrupt Flags
    493
  - Eusci_A UART Registers
    494
  - Ucaxctlw0 Register
    495
  - Ucaxctlw0 Register Description
    495
  - Ucaxctlw1 Register
    496
  - Ucaxctlw1 Register Description
    496
  - Ucaxctlw0 Register Description
    496
  - Ucaxbrw Register
    497
  - Ucaxmctlw Register
    497
  - Ucaxbrw Register Description
    497
  - Ucaxmctlw Register Description
    497
  - Ucaxstatw Register
    498
  - Ucaxstatw Register Description
    498
  - Ucaxrxbuf Register
    499
  - Ucaxtxbuf Register
    499
  - Ucaxrxbuf Register Description
    499
  - Ucaxtxbuf Register Description
    499
  - Ucaxabctl Register
    500
  - Ucaxabctl Register Description
    500
  - Ucaxirctl Register
    501
  - Ucaxirctl Register Description
    501
  - Ucaxie Register
    502
  - Ucaxie Register Description
    502
  - Ucaxifg Register
    503
  - Ucaxifg Register Description
    503
  - Ucaxiv Register
    504
  - Ucaxiv Register Description
    504
  - Eusci Block Diagram - SPI Mode
    507
  - Ucxste Operation
    508
  - Eusci Master and External Slave (UCSTEM = 0)
    509
  - Eusci Slave and External Master
    510
  - Eusci SPI Timing with UCMSB
    512
  - Eusci_A SPI Registers
    514
  - Ucaxctlw0 Register
    515
  - Ucaxbrw Register
    517
  - Ucaxbrw Register Description
    517
  - Ucaxstatw Register
    518
  - Ucaxstatw Register Description
    518
  - Ucaxrxbuf Register
    519
  - Ucaxrxbuf Register Description
    519
  - Ucaxtxbuf Register
    520
  - Ucaxtxbuf Register Description
    520
  - Ucaxie Register
    521
  - Ucaxie Register Description
    521
  - Ucaxifg Register
    522
  - Ucaxifg Register Description
    522
  - Ucaxiv Register Description
    523
    
    Ucaxiv Register 19.5 Eusci_B SPI Registers
    524
  - Eusci_B SPI Registers
    524
    
    Ucbxctlw0 Register
    525
  - Ucbxctlw0 Register Description
    525
  - Ucbxctlw0 Register Description
    526
    
    Ucbxbrw Register
    527
    
    Ucbxstatw Register
    527
  - Ucbxbrw Register Description
    527
  - Ucbxstatw Register Description
    527
    
    Ucbxrxbuf Register
    528
    
    Ucbxtxbuf Register
    528
  - Ucbxrxbuf Register Description
    528
  - Ucbxtxbuf Register Description
    528
    
    Ucbxie Register
    529
    
    Ucbxifg Register
    529
  - Ucbxie Register Description
    529
  - Ucbxifg Register Description
    529
    
    Ucbxiv Register
    530
  - Ucbxiv Register Description
    530
- Enhanced Universal Serial Communication Interface (Eusci) - I 2 C Mode
  
  531
  - Enhanced Universal Serial Communication Interface B (Eusci_B) Overview
    532
  - Mode
    532
  - Mode
    533
  - Eusci_B Block Diagram - I
    533
    
    Bus Connection Diagram
    534
    
    Eusci_B Initialization and Reset
    534
    
    I 2 C Serial Data
    534
    
    Addressing Modes
    535
    
    Module Data Transfer
    535
  - Bit Transfer on I
    535
    
    Module 7-Bit Addressing Format
    535
  - I2C Master 10-Bit Addressing Mode
    535
    
    I 2 C Quick Setup
    536
    
    Module 10-Bit Addressing Format
    536
  - C Module Addressing Format with Repeated START Condition
    536
    
    Module Operating Modes
    537
    
    Slave Transmitter Mode
    538
    
    Time-Line Legend
    538
  - C Slave Receiver Mode
    539
  - C Slave 10-Bit Addressing Mode
    540
  - C Master Transmitter Mode
    542
  - I 2 C Master Receiver Mode
    544
  - Arbitration Procedure between Two Master Transmitters
    546
    
    Glitch Filtering
    547
  - Synchronization of Two I
    547
    
    Clock Generators During Arbitration
    547
  - Glitch Filter Length Selection Bits
    547
    
    C Clock Generation and Synchronization 20.3.8 Byte Counter
    548
    
    Mode with Low-Power Modes
    549
    
    Multiple Slave Addresses
    549
    
    Eusci_B Interrupts in I C Mode
    550
    
    Eusci_B I2C Registers
    553
    
    Ucbxctlw0 Register
    554
    
    Ucbxctlw1 Register
    556
  - Ucbxctlw1 Register Description
    556
    
    Ucbxbrw Register
    558
    
    Ucbxstatw
    558
  - Ucbxstatw Register
    558
  - Ucbxbrw Register Description
    558
    
    Ucbxtbcnt Register
    559
  - Ucbxtbcnt Register Description
    559
    
    Ucbxrxbuf Register
    560
    
    Ucbxtxbuf
    560
  - Ucbxtxbuf Register
    560
    
    Ucbxi2Coa0 Register
    561
    
    Ucbxi2Coa1 Register
    562
    
    Ucbxi2Coa2 Register
    562
    
    Ucbxaddrx Register
    563
    
    Ucbxi2Coa3 Register
    563
    
    Ucbxaddmask Register
    564
    
    Ucbxi2Csa Register
    564
  - Ucbxi2Csa Register Description
    564
    
    Ucbxie Register
    565
  - Ucbxie Register Description
    565
    
    Ucbxifg Register
    567
  - Ucbxifg Register Description
    567
    
    Ucbxiv Register
    569
  - Ucbxiv Register Description
    569
- Embedded Emulation Module (EEM)
  
  570
  - EEM Configurations
    570
    
    Embedded Emulation Module (EEM) Introduction
    571
  - Large Implementation of EEM
    572
    
    Cycle Counter
    573
    
    EEM Building Blocks
    573
    
    State Storage (Internal Trace Buffer)
    573
    
    Trigger Sequencer
    573
    
    Triggers
    573
    
    Clock Control
    574
    
    EEM Configurations
    574
- Revision History
  
  575

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