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Lucent Technologies DSP1618 Information Manual

Lucent Technologies DSP1618 Information Manual (443 pages)

Digital Signal Processor

Brand: Lucent Technologies | Category: Computer Hardware | Size: 4.55 MB

Table of Contents

Dsp1611/17/18/27/28/29 Digital Signal Processor

4
Software Architecture

53
Chapter 4 Instruction Set

117
Chapter 5 Core Architecture

155
- Core Architecture
  156
- Data Arithmetic Unit
  156
- Figure 5-1.DAU-Data Arithmetic Unit
  156
- Alu
  157
- Inputs and Outputs
  157
- Multiplier Functions
  157
- Accumulators
  158
- Counters
  159
- Figure 5-2.Conditional Instructions Using Counter Conditionals
  159
- Table 5-1. Counter Conditionals
  159
- Figure 5-3.The Ifc con F2 Instruction
  161
- Table 5-2. C0-C2 Register Functions
  161
- DAU Pseudorandom Sequence Generator (PSG)
  162
- Figure 5-4.DAU Pseudorandom Sequence Generator
  163
- Control Registers
  164
- Table 5-3. Arithmetic Unit Control (Auc) Register
  164
- Control Registers
  165
- Table 5-4. Processor Status Word (Psw) Register
  165
- Address Arithmetic Unit (XAAU)
  166
  - Inputs and Outputs
    166
  - X-Memory Space Segment Selection
    166
  - Figure 5-5.XAAU-X Address Arithmetic Unit
    166
  - Register Descriptions
    167
- Y Address Arithmetic Unit (YAAU)
  167
  - Inputs and Outputs
    168
  - Figure 5-6.YAAU-Y Address Arithmetic Unit
    168
- Y Address Arithmetic Unit (YAAU)
  168
  - Y-Memory Space
    169
  - Register Descriptions
    169
  - Addressing Modes
    169
  - Figure 5-7.Direct Data Addressing
    170
  - Figure 5-8.Use of the Rb and Re Registers
    171
- Cache and Control
  172
- External Memory Interface
  176
Chapter 6 External Memory Interface

177
Chapter 7 Serial I\/O

209
Chapter 8 Parallel I\/O (Dsp1617 Only)

238
- Figure 8-1.Parallel I/O Unit
  239
  - Parallel I/O (DSP1617 Only)
    239
  - PIO Operation
    240
    
    Active Mode
    240
    
    Table 8-1. PIO Strobe Widths
    240
    
    Figure 8-2.Active Mode Input Timing (Minimum Width PIDS)
    241
  - Programmer Interface
    252
  - Table 8-5. Port Encoding Pdx<0-7
    252
  - Table 8-6. PIO Control (Pioc) Register
    253
    
    Pioc Register Settings
    254
    
    Latent Reads
    255
    
    Figure 8-11.PIO Latent Reads Hardware
    256
    
    Figure 8-12.PIO Latent Reads Timing
    256
    
    Power Management
    257
  - Interrupts and the PIO
    257
  - PIO Signals
    259
    
    PIO Pin Multiplexing
    260
  - PIO Loopback Test Mode
    260
  - Table 8-7. PIO Signals
    260
  - Table 8-8. PIO Pin Multiplexing
    260
- Active Mode
  241
- Figure 8-3.Active Mode Output Timing (Minimum Width PODS)
  242
- Figure 8-4.PIO Interaccess Timing
  243
- PIO Interaccess Timing
  243
- Passive Mode
  244
- Peripheral Mode (Host Interface)
  244
- Table 8-2. Function of the PSEL Pins
  244
- Figure 8-5.Passive Mode Input Timing
  245
- Figure 8-6.Passive Mode Output Timing
  246
- Figure 8-7.The DSP as a Microprocessor Peripheral
  247
- Table 8-3. the PIO Status Register, PSTAT
  248
- Table 8-4. the PIO Buffer Flags
  248
- Figure 8-8.Peripheral Mode Input Timing
  249
- Figure 8-9.Peripheral Output Mode Timing
  250
- Figure 8-10.Polling PSTAT Timing
  251
- Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
  261
Chapter 9 Parallel Host Interface (Phif) (Dsp1611/18/27/28/29 Only)

262
- Figure 9-1.Parallel Host Interface
  262
- Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
  263
- PHIF Operation
  264
  - Intel Mode, 16-Bit Read
    265
  - Figure 9-2. Intel Mode, 16-Bit Read
    265
  - Intel Mode, 16-Bit Write
    266
  - Figure 9-3. Intel Mode, 16-Bit Write
    266
  - Motorola Mode, 16-Bit Read
    267
  - Figure 9-4. Motorola Mode, 16-Bit Read
    267
  - Motorola Mode, 16-Bit Write
    268
  - Figure 9-5. Motorola Mode, 16-Bit Write
    268
  - 8-Bit Transfers
    269
  - Accessing the PSTAT Register
    269
  - Table 9-1. the PHIF Status Register, PSTAT
    269
- Programmer Interface
  270
- Interrupts and the PHIF
  272
- PHIF Pin Multiplexing
  273
- Table 9-4. PHIF Pin Multiplexing of Active Signals
  273
- Figure 9-6.Overall PHIF Read Cycle
  274
- Overall Functional Timing
  274
Chapter 10 Bit I\/O Unit

276
- BIO Hardware Function
  277
- Bit I/O Unit
  277
  - BIO Configured as Inputs
    278
  - BIO Configured as Outputs
    278
  - Figure 10-2.BIO Configured as Inputs
    278
- Figure 10-1.BIO Block Diagram
  277
- BIO Hardware Function
  278
- Figure 10-3.BIO Configured as Outputs
  279
- Pin Descriptions
  279
- BIO Pin Multiplexing
  280
- Figure 10-4.Logic Flow Diagram for BIO Configuration
  280
- Software View
  280
- Table 10-1. BIO Pin Multiplexing
  280
  - Registers
    281
  - Table 10-2. Sbit Register Encoding
    281
  - Table 10-3. Cbit Register Encoding
    281
  - Flags
    282
  - Instructions
    282
  - Examples
    282
  - Table 10-4. Alf Flags
    282
Chapter 11 Jtag Test Access Port

285
Chapter 12 Timer

307
- Figure 12-1.Timer Block Diagram
  308
- Hardware View
  308
- Programmable Features and Operation
  309
  - Timerc Register Encoding
    309
  - Table 12-1. Timerc Register
    309
- Timer
  309
  - Timer0 Register
    310
  - The Inc Register
    310
  - Initialization Conditions
    310
- Program Example
  311
- Figure 12-2.Timing Examples
  312
- Timing
  312
Chapter 13 Bit Manipulation Unit

314
- Bit Manipulation Unit (BMU)
  315
  - Hardware View
    315
  - Figure 13-1.BMU Block Diagram
    315
  - Software View
    316
    
    Figure 13-2.Logical Right Shift
    316
    
    Instruction Set
    316
    
    Shifting Operations
    316
    
    Figure 13-3.Left Shifts
    317
    
    Figure 13-4.Arithmetic Right Shift
    317
  - Bit Manipulation Unit (BMU)
    317
    
    Shifting Operations
    317
    
    Software View
    317
    
    Normalization
    318
    
    Extraction
    319
    
    Figure 13-5.Extraction
    319
    
    Figure 13-6.Insertion, Case 1. Source and Destination Accumulators Different
    320
    
    Insertion
    320
    
    Figure 13-7.Insertion, Case 2. Source and Destination Accumulators Are the same
    321
    
    Figure 13-8.Shuffle Accumulators
    322
    
    Shuffle Accumulators
    322
    
    Instruction Encoding
    323
    
    Table 13-1. Format 3B: BMU Operations
    323
    
    Software Example
    324
Chapter 14 Error Correction Coprocessor (Dsp1618/28 Only)

326
- Error Correction Coprocessor (DSP1618/28 Only)
  327
- System Description
  327
- Figure 14-1.Error Correction Coprocessor Block Diagram/Programming Model
  328
  - System Description
    328
- Hardware Architecture
  329
  - Branch Metric Unit
    329
  - Update Unit
    330
  - Traceback Unit
    330
  - Table 14-1. Incremental Branch Metrics
    330
  - Interrupts and Flags
    331
  - Traceback RAM
    331
- DSP Decoding Operation Sequence
  332
- Figure 14-2.DSP Core Operation Sequence
  332
- Figure 14-3.ECCP Operation Sequence
  333
- Operation of the ECCP
  333
- Software Architecture
  334
  - R-Field Registers
    334
  - Figure 14-4.Register Block Diagram
    334
  - Table 14-2. ECCP Instruction Encoding
    335
  - Table 14-3. Reset State of ECCP Registers
    335
  - ECCP Internal Memory-Mapped Registers
    336
  - Table 14-4. Memory-Mapped Registers
    336
  - Table 14-5. Control Fields of the Control Register
    338
  - ECCP Interrupts and Flags
    343
  - Traceback RAM
    343
- ECCP Instruction Timing
  345
- Interface Guide
  350
  - Pin Information
    352
  - Table 15-1. DSP1611/17/18 Pin Descriptions (See Footnotes for any DSP1611/18 Differences.)
    352
  - Table 15-2. DSP1627/28/29 Pin Descriptions
    354
  - Signal Descriptions
    356
    
    System Interface
    356
    
    External Memory Interface
    357
    
    Serial Interface #1
    358
    
    PIO/PHIF or Serial Interface #2 and Control I/O Interface
    360
    
    Control I/O Interface
    362
    
    JTAG Test Interface
    362
  - Resetting DSP161X and DSP162X Devices
    363
    
    Powerup Reset
    363
    
    Using the TAP to Reset the TAP Controller
    363
    
    RSTB Pin Reset
    364
  - Mask-Programmable Options
    365
    
    Input Clock Options
    365
    
    ROM Security Options (DSP1617/18/27/28/29 Only)
    365
    
    Table 15-3. DSP1617/18/27/28/29 ROM Options
    365
    
    Table 15-4. DSP1611 Input Clock Options
    365
  - Additional Electrical Characteristics and Requirements for Crystal
    366
- A Instruction Encoding
  369
  - Instruction Encoding Formats
    371
- Table A-2. B Field
  372
- Table A-3. BMU Encodings
  372
  - Field Descriptions
    373
- Table A-4. con Field
  373
- Table A-5. D Field
  373
- Table A-6. DR Field
  373
- Table A-7. F1 Field
  374
- Table A-8. F2 Field
  374
- Table A-10. I Field
  375
- Table A-9. F3 Field
  375
- Table A-11. R Field for DSP1617
  376
- Table A-12. R Field for DSP1611/18/27/28/29
  376
- Table A-13. S Field
  377
- Table A-14. si Field
  377
- Table A-15. SRC2 Field
  377
- Table A-16. T-Field
  377
- Table A-17. X Field
  378
- Table A-18. y Field
  378
- Table A-19. Z Field
  378
Appendix B

380
- Appendix B. Instruction Set Summary
  382
  - B Instruction Set Summary
    382
    
    Goto JA
    382
  - Goto B
    383
  - If con Goto/Call/Return
    384
  - Table B-1. con Field Encoding
    384
    
    Call JA
    385
    
    Icall
    386
    
    Do K
    387
    
    Redo K
    388
    
    R = Im16
    389
  - Table B-2. R Field Replacement Values
    389
    
    Sr = Im9
    391
    
    R = As[L
    392
    
    At[L] = R
    393
    
    R = y
    394
    
    Y = R
    395
    
    Z : R
    396
    
    Dr = *(Offset
    397
    
    (Offset) = Dr
    398
    
    If con F2
    399
    
    Ifc con F2
    400
    
    F1 y
    401
    
    F1 y = A0[L
    403
    
    F1 y = A1[L
    403
  - F1 y = A0[L
    404
  - F1 y = A1[L
    404
    
    F1 X = y
    405
  - F1 X = y
    406
    
    F1 Y[L] = y
    407
  - F1 Y[L] = y
    408
    
    F1 y = y X = *Pt++[I
    409
  - F1 y = y X = *Pt++[I
    410
    
    F1 y = A0 X = *Pt++[I
    411
    
    F1 y = A1 X = *Pt++[I
    411
  - F1 y = A0 X = *Pt++[I
    412
  - F1 y = A1 X = *Pt++[I
    412
    
    F1 At[L] = y
    413
  - F1 At[L] = y
    414
    
    F1 y = Y[L
    415
  - F1 y = Y[L
    416
    
    F1 Z : Y[L
    417
  - F1 Z : Y[L
    418
  - F1 Z : At[L
    419
  - F1 Z : At[L
    420
  - F1 Z : y X = *Pt++[I
    421
  - F1 Z : y X = *Pt++[I
    422
  - Ad = as OP at
    423
  - Ad = as OP P
    424
  - Ad = As<H,L> OP IM16
    425
  - Ad = a SHIFT as
    427
  - Ad = as SHIFT Arm
    428
  - Ad = as SHIFT IM16
    429
  - Ad = Exp (as
    430
  - Ad = Norm (As, Arm
    431
  - Ad = Extracts (As, Arm
    432
  - Ad = Extractz (As, Arm
    432
  - Ad = Extracts (As, IM16
    433
  - Ad = Extractz (As, IM16
    433
  - Ad = Insert (As, Arm
    434
  - Ad = Insert (As, IM16
    435
  - Ad = as : Aat
    436

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