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JUNOS 10.1 - S REV 4
Juniper JUNOS 10.1 - S REV 4 Manuals
Manuals and User Guides for Juniper JUNOS 10.1 - S REV 4. We have
3
Juniper JUNOS 10.1 - S REV 4 manuals available for free PDF download: Configuration Manual, Release Note
Juniper JUNOS 10.1 - S REV 4 Configuration Manual (1654 pages)
Network Interfaces Configuration
Brand:
Juniper
| Category:
Software
| Size: 10.66 MB
Table of Contents
List of Figures
55
List of Tables
59
About this Guide Lxiii
63
Audience on Page Lxiv
63
JUNOS Documentation and Release Notes
63
Objectives on Page Lxiv
63
Supported Routing Platforms on Page Lxiv
63
Using the Examples in this Manual on Page Lxv
63
Merging a Full Example
65
Merging a Snippet
66
Using the Indexes on Page Lxv
63
Documentation Conventions
66
Table 1: Notice Icons
67
Table 2: Text and Syntax Conventions
67
Documentation Feedback
68
Requesting Technical Support
68
Self-Help Online Tools and Resources
69
Opening a Case with JTAC
69
Part 1 Network Interfaces Configuration Statements Overview
71
Chapter 1 Network Interfaces Configuration Statements and Hierarchy
73
Network Interfaces Configuration Statements and Hierarchy
73
[Edit Chassis] Hierarchy Level
73
[Edit Interfaces] Hierarchy Level
77
[Edit Protocols Connections] Hierarchy Level
94
[Edit Protocols Dot1X] Hierarchy Level
95
Part 2 Router Interfaces Configuration Concepts
99
Chapter 2 Understanding Router Interfaces
99
Chapter 2 Understanding Router Interfaces
101
Figure 2: Container Interface
101
Router Interfaces Overview
102
Types of Interfaces Overview
102
Permanent Interfaces Overview
103
Understanding Management Ethernet Interfaces
103
Understanding Internal Ethernet Interfaces
104
Understanding Services Interfaces
106
Understanding Transient Interfaces
106
Container Interfaces Overview
108
Understanding Traditional APS Concept
108
Container Interfaces Concept
108
APS Support for Container-Based Interfaces
108
Autocopy of APS Parameters
108
Figure 1: APS Interface
108
Interface Encapsulations Overview
110
Table 3: Encapsulation Support by Interface Type
110
Interface Descriptors Overview
121
Interface Naming Overview
122
Interface Naming for a Routing Matrix Based on a TX Matrix Router
123
Interface Naming for a Routing Matrix Based on a TX Matrix Plus
123
Router
123
Chassis Interface Naming
123
Examples: Interface Naming
123
Figure 3: Routing Matrix
129
Table 4: FPC Numbering for T640 Routers in a Routing Matrix
130
Table 5: One-To-One FPC Numbering for T640 Routers in a Routing Matrix
130
Figure 4: Routing Matrix Based on a TX Matrix Plus Router
131
Table 6: FPC Numbering for T1600 Routers in a Routing Matrix
132
Table 7: One-To-One FPC Numbering for T1600 Routers in a Routing Matrix
132
Figure 5: Interface Slot, PIC, and Port Locations
134
Displaying Interface Configurations Overview
135
Interface and Router Clock Sources Overview
135
Interface and Router Clock Sources Description
135
Configuring an External Synchronization Interface
135
Figure 6: Clock Sources
136
Configuring Physical Interface Properties
139
Physical Interface Configuration Statements Overview
140
Physical Interfaces Properties Statements List
149
Table 8: Statements for Physical Interface Properties
149
Interface Ranges
165
Configuring Interface Ranges
165
Expanding Interface Range Member and Member Range Statements
165
Configuration Inheritance for Member Interfaces
165
Member Interfaces Inheriting Configuration from Configuration
165
Groups
171
Interfaces Inheriting Common Configuration
172
Configuring Inheritance Range Priorities
173
Configuration Expansion Where Interface Range Is Used
173
Specifying an Aggregated Interface
174
Specifying a USB Modem Interface on J Series Routers
175
Specifying OC768-Over-OC192 Mode
177
Adding an Interface Description to the Configuration
178
Example: Adding an Interface Description to the Configuration
178
Configuring the Link Characteristics
179
Table 10: Media MTU Sizes by Interface Type for M40E Routers
180
Table 9: Media MTU Sizes by Interface Type for M5, M7I with CFEB, M10, M10I with CFEB, M20, and M40 Routers
180
Table 11: Media MTU Sizes by Interface Type for M160 Routers
181
Table 12: Media MTU Sizes by Interface Type for M7I with CFEB-E, M10I with CFEB-E, M320 and M120 Routers
182
Table 13: Media MTU Sizes by Interface Type for T320 Routers
183
Table 14: Media MTU Sizes by Interface Type for T640 Platforms
183
Table 15: Media MTU Sizes by Interface Type for J2300 Platforms
183
Table 16: Media MTU Sizes by Interface Type for J4300 and J6300 Platforms
184
Table 17: Media MTU Sizes by Interface Type for J4350 and J6350 Platforms
184
Table 18: Encapsulation Overhead by Encapsulation Type
186
Configuring Interface Encapsulation on Physical Interfaces
188
Configuring the Encapsulation on a Physical Interface
188
Encapsulation Capabilities
192
Example: Configuring the Encapsulation on a Physical Interface
193
Configuring the PPP Challenge Handshake Authentication Protocol
194
Assigning an Access Profile to an Interface
194
Configuring a Default CHAP Secret
194
Configuring the Local Name
195
Configuring Passive Mode
195
Example: Configuring the PPP Challenge Handshake Authentication Protocol
195
Configuring the PPP Password Authentication Protocol
196
Configuring the Local Name
198
Configuring the Local Password
198
Configuring Passive Mode
199
Example: Configuring PAP Authentication Protocol
199
Monitoring a PPP Session
200
Tracing Operations of the Pppd Process
201
Configuring PPP Address and Control Field Compression
202
Configuring the PPP Protocol Field Compression
203
Configuring the Interface Speed
204
Management Ethernet Interface on M Series and T Series Routers
204
Gigabit Ethernet Interfaces on J Series Routers
204
Fast Ethernet Interface
204
Tri-Rate Ethernet Copper Interface
204
SONET/SDH Interface
204
Table 19: Type 1 PIC Mode Combinations
207
Table 20: Type 2 PIC Mode Combinations
207
Configuring Keepalives
208
Configuring the Clock Source
210
Configuring the Router as a DCE
210
Configuring Receive and Transmit Leaky Bucket Properties
211
Configuring Accounting for the Physical Interface
212
Applying an Accounting Profile to the Physical Interface
212
Example: Applying an Accounting Profile to the Physical Interface
213
Interface Diagnostics
213
Configuring Loopback Testing
213
Table 21: Loopback Modes by Interface Type
214
Interface Diagnostics
216
Starting and Stopping a BERT Test
218
Table 22: BERT Capabilities by Interface Type
218
Example: Configuring Bit Error Rate Testing
219
Tracing Operations of an Individual Router Interface
219
Configuring Multiservice Physical Interface Properties
220
Damping Interface Transitions
220
Enabling or Disabling SNMP Notifications on Physical Interfaces
221
Enabling Unidirectional Traffic Flow on Physical Interfaces
221
Disabling a Physical Interface
222
Example: Disabling a Physical Interface
223
Chapter 4 Configuring Logical Interface Properties
225
Configuring Logical Interface Properties
227
Logical Interfaces Configuration Statements
227
Logical Interfaces Statements List
229
Table 23: Statements for Logical Interface Properties
229
Configuring Logical System Interface Properties
236
Example: Configuring Logical System Interface Properties
237
Specifying the Logical Interface Number
236
Adding a Logical Unit Description to the Configuration
238
Configuring a Point-To-Point Connection
238
Configuring a Multipoint Connection
239
Configuring Accounting for the Logical Interface
239
Applying an Accounting Profile to the Logical Interface
239
Example: Applying an Accounting Profile to the Logical Interface
240
Configuring the Interface Bandwidth
240
Configuring Interface Encapsulation on Logical Interfaces
241
Configuring the Encapsulation on a Logical Interface
241
Enabling or Disabling SNMP Notifications on Logical Interfaces
241
Configuring the LCP Configure-Request Maximum Sent
243
Configuring the NCP Configure-Request Maximum Sent
243
Configuring the PPP Restart Timers
243
Configuring Dynamic Profiles for PPP
244
Configuring the PPP Clear Loop Detected Timer
244
Configuring PPP CHAP Authentication
245
Configuring PPP PAP Authentication
245
Configuring a Default PAP Password
246
Configuring the Local Name
246
Configuring the Local Password
247
Configuring Passive Mode
247
Configuring Dynamic Call Admission Control
247
Example: Configuring Dynamic CAC
248
Disabling a Logical Interface
249
Configuring Protocol Family and Interface Address Properties
251
Protocol Family Configuration and Interface Address Statements
251
Chapter 5 Configuring Protocol Family and Interface Address Properties
253
Configuring the Protocol Family
255
Ipv6 Overview
255
Ipv4-To-Ipv6 Transition
255
VRRP Properties
256
Configuring the Interface Address
256
Configuring an Interface Ipv4 Address
257
Configuring the Interface Ipv6 Address
257
Configuring ICCP for MC-LAG
258
Configuring IPCP Options
259
Configuring an IP Address for an Interface
260
Negotiating an IP Address Assignment from the Remote End
260
Configuring an Interface to be Unnumbered
260
Assigning a Destination Profile to the Remote End
260
Configuring an Unnumbered Interface
262
Configuring an Unnumbered Point-To-Point Interface
262
Example: Configuring an Unnumbered Point-To-Point Interface
262
Configuring an Unnumbered Ethernet or Demux Interface
262
Configuring a Preferred Source Address for Unnumbered Ethernet or Demux Interfaces
264
Configuring Static Routes on Unnumbered Ethernet Interfaces
264
Restrictions for Configuring Unnumbered Ethernet Interfaces
265
Unnumbered Ethernet Interface
265
Example: Configuring an Unnumbered Ethernet Interface as the Next Hop for a Static Route
267
Setting the Protocol MTU
267
Disabling the Removal of Address and Control Bytes
268
Disabling the Transmission of Redirect Messages on an Interface
268
Configuring Default, Primary, and Preferred Addresses and Interfaces
269
Configuring the Primary Interface for the Router
269
Configuring the Primary Address for an Interface
269
Configuring the Preferred Address for an Interface
269
Applying Policers
271
Applying Aggregate Policers
272
Example: Applying Aggregate Policers
273
Applying Hierarchical Policers on Enhanced Intelligent Queuing Pics
274
Figure 7: Hierarchical Policer
275
Hierarchical Policer Overview
275
Hierarchical Policing Characteristics
275
Configuring Hierarchical Policers
276
Configuring a Single-Rate Tricolor Policer
277
Configuring a Single-Rate Two-Color Policer
277
Configuring a Two-Rate Tricolor Marker Policer
278
Applying a Filter to an Interface
280
Defining Interface Groups in Firewall Filters
282
Filter-Based Forwarding on the Output Interface
282
Example: Applying a Filter to an Interface
282
Configuring Unicast RPF
285
Configuring Unicast RPF Strict Mode
285
Configuring Unicast RPF Loose Mode
285
Unicast RPF and Default Routes
285
Unicast RPF Behavior with a Default Route
287
Unicast RPF Behavior Without a Default Route
287
Unicast RPF with Routing Asymmetry
288
Figure 8: Unicast RPF with Routing Asymmetry
288
Configuring Unicast RPF on a VPN
289
Example: Configuring Unicast RPF on a VPN
289
Example: Configuring Unicast RPF
289
Enabling Source Class and Destination Class Usage
290
Figure 9: Prefix Accounting with Source and Destination Classes
291
Examples: Enabling Source Class and Destination Class Usage
293
Chapter 6 Configuring Circuit and Translational Cross-Connects
299
Figure 10: Layer 2 Switching Circuit Cross-Connect
300
Configuring ATM-To-Ethernet Interworking
306
Enabling ATM-To-Ethernet Interworking
306
Configuring the ATM-To-Ethernet Interworking Ethernet Interface
306
Configuring the ATM-To-Ethernet Interworking Ethernet Encapsulation
306
Configuring the ATM-To-Ethernet Interworking Outer VLAN Identifier
306
Configuring the ATM-To-Ethernet Interworking Inner VLAN Identifier
306
Range
306
Configuring the ATM-To-Ethernet Interworking Physical Interface VPI
306
Configuring the ATM-To-Ethernet Interworking ATM Logical Interface
306
Configuring the ATM-To-Ethernet Interworking Protocol Family
307
Configuring the ATM-To-Ethernet Interworking Logical Interface VPI
307
Configuring the ATM-To-Ethernet Interworking Logical Interface VCI
307
Examples: Configuring Switching Cross-Connects
309
Example: Configuring a CCC over Frame Relay Encapsulated Interface
310
Example: Configuring a TCC
310
Figure 11: Example Topology of a Switching Circuit Cross-Connect with Frame Relay CCC Encapsulation
310
Figure 12: Layer 2.5 Switching Translational Cross-Connect
311
Example: Configuring CCC over Aggregated Ethernet
312
Figure 13: Interface-To-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces
312
Example: Configuring a Remote LSP CCC over Aggregated Ethernet
314
Figure 14: Remote Interface-LSP-Interface Circuit Cross-Connect over Aggregated Ethernet Interfaces
314
Example: Configuring ATM-To-Ethernet Interworking
316
Figure 15: ATM-To-Ethernet Interworking
316
Tracing Interface Operations
317
Tracing Interface Operations Overview
317
Tracing Operations of an Individual Router Interface
317
Tracing Operations of the Interface Process
318
Part 3 Configuring Special Router Interfaces
319
Displaying Internal Ethernet Interfaces for a Routing Matrix with a TX Matrix
321
Plus Router
321
Displaying the Internal Ethernet Interface
321
Displaying the Internal Ethernet Interface for M Series, MX Series, and most T Series Routers
321
Internal Ethernet Interface Overview
321
Configuring Discard Interfaces
325
Discard Interfaces Overview
325
Example: Discard Interface
325
Configuring an IP Demultiplexing Interface
327
Configuring an IP Demux Underlying Interface
327
Configuring IP Demultiplexing Interfaces
327
IP Demultiplexing Interface Overview
327
Specifying the Demux Underlying Interface
329
Configuring IP Demux Prefixes
330
Configuring MAC Address Validation on Static Demux Interfaces
330
Example: Configuring a Demux Interface
331
Configuring the Loopback Interface
333
Example: Configuring the Loopback Interface
334
Configuring Serial Interfaces
337
Chapter 12 Configuring Serial Interfaces
339
Serial Interface Default Settings
342
Interface Default Settings
342
Invalid Serial Interface Statements
342
Invalid EIA-530 Interface Statements
343
Invalid V.35 Interface Statements
343
Invalid X.21 Interface Statements
343
Configuring the Serial Line Protocol
339
Example: Physical Interface Configuration Statements for Serial Interfaces
339
Serial Interfaces Overview
339
Configuring the Serial Clocking Mode
345
Figure 16: Serial Interface Clocking Mode
345
Configuring the DTE Clock Rate
346
Inverting the Serial Interface Transmit Clock
346
Configuring the Serial Idle Cycle Flag
347
Configuring the Serial Signal Handling
348
Table 24: Signal Handling by Serial Interface Type
348
Configuring the Serial DTR Circuit
350
Configuring Serial Loopback Capability
351
Configuring Serial Signal Polarities
351
Figure 17: Serial Interface LIU Loopback
352
Figure 18: Serial Interface Local Loopback
352
Configuring Serial Line Encoding
353
Example: Configuring Serial Loopback Capability
353
Part 5 Configuring ATM Interfaces
355
Configuring ATM Interfaces
356
ATM Interfaces Overview
357
ATM1 Physical and Logical Configuration Statement Hierarchies
357
ATM2 IQ Physical and Logical Configuration Statement Hierarchies
357
Chapter 13 Configuring ATM Interfaces
357
Table 25: ATM1 and ATM2 IQ Supported Features
364
Example: Configuring Communication with Directly Attached ATM Switches and Routers
369
Configuring Communication with Directly Attached ATM Switches and
357
Supported Features on ATM1 and ATM2 IQ Interfaces
357
Enabling ILMI for Cell Relay
370
Table 26: ILMI Support by Encapsulation Type
370
Example: Enabling ILMI for Cell Relay
371
Enabling Passive Monitoring on ATM Interfaces
371
Removing MPLS Labels from Incoming Packets
372
Configuring the ATM PIC Type
373
Example: Configuring the ATM PIC Type
373
Configuring ATM Cell-Relay Promiscuous Mode
374
Examples: Configuring ATM Cell-Relay Promiscuous Mode
375
Configuring the Maximum Number of ATM1 Vcs on a VP
377
Configuring Layer 2 Circuit Transport Mode
378
Examples: Configuring IQ Layer 2 Circuit Transport Mode
380
Figure 19: Layer 2 Circuit Trunk Topology
382
Configuring Layer 2 Circuit Cell-Relay Promiscuous Mode
386
Example: Configuring Layer 2 Circuit Cell-Relay Promiscuous Mode
386
Configuring Layer 2 Circuit Trunk Mode Scheduling
387
Example: Configuring Layer 2 Circuit Trunk Mode Scheduling
387
Configuring Cos Queues in Layer 2 Circuit Trunk Mode
388
Example: Configuring Cos Queues in Layer 2 Circuit Trunk Mode
390
Configuring the Layer 2 Circuit Cell-Relay Cell Maximum
391
Class-Based Cell Bundling
392
Configuring the OAM F4 Cell Flows
392
Configuring a Point-To-Point ATM1 or ATM2 IQ Connection
394
Defining Virtual Path Tunnels
394
Configuring a Point-To-Multipoint ATM1 or ATM2 IQ Connection
395
Configuring a Multicast-Capable ATM1 or ATM2 IQ Connection
396
Configuring Inverse ATM1 or ATM2 ARP
396
Defining the ATM Traffic-Shaping Profile
396
Configuring ATM CBR
397
Configuring ATM2 IQ Real-Time VBR
397
Configuring ATM VBR
397
Specifying ATM1 Shaping Values
397
Table 27: Shaping Rate Range by Interface Type
398
Example: Specifying ATM1 Shaping Values
401
Table 28: ATM1 Traffic-Shaping Rates
401
Specifying Atm2 Iq Shaping Values
402
Configuring the ATM1 Queue Length
403
Configuring the ATM2 IQ EPD Threshold
404
Example: Configuring the ATM2 IQ EPD Threshold
405
Table 29: EPD Threshold Range by Interface Type
405
Configuring the ATM2 IQ Transmission Weight
406
Configuring Two EPD Thresholds Per Queue
406
Configuring the ATM OAM F5 Loopback Cell Threshold
407
Defining the ATM OAM F5 Loopback Cell Period
407
Configuring ATM Interface Encapsulation
408
Table 30: ATM Logical Interface Encapsulation Types
409
Configuring an ATM1 Cell-Relay Circuit
410
Example: Configuring an ATM1 Cell-Relay Circuit
410
Configuring PPP over ATM2 Encapsulation
412
Example: Configuring Ppp over Atm2 Iq Encapsulation
413
Configuring E3 and T3 Parameters on ATM Interfaces
415
Configuring SONET/SDH Parameters on ATM Interfaces
416
Configuring ATM2 IQ VC Tunnel Cos Components
417
Example: Enabling Eight Queues on T Series, M120, and M320 Platforms
421
Figure 20: Example Topology for Router with Eight Queues
421
Configuring VC Cos Mode
426
Enabling the PLP Setting to be Copied to the CLP Bit
426
Configuring ATM Cos on the Logical Interface
427
Example: Configuring ATM2 IQ VC Tunnel Cos Components
427
Example: Configuring ATM1 Interfaces
428
Example: Configuring ATM2 IQ Interfaces
430
ATM-Over-ADSL Overview
433
Configuring ATM-Over-ADSL Interfaces
433
Configuring Physical ATM Interfaces and Logical Interface Properties for ADSL
433
Configuring the ATM-Over-ADSL Logical Interface Encapsulation Type
433
Configuring the ATM-Over-ADSL Physical Interface Encapsulation Type
433
Configuring the ATM-Over-ADSL Physical Interface Operating Mode
433
Configuring the ATM-Over-ADSL Protocol Family
433
Configuring the ATM-Over-ADSL Virtual Channel Identifier
433
Configuring the ATM-Over-ADSL Virtual Path Identifier
433
Table 31: ATM-Over-ADSL Operational Modes
435
Table 32: ATM-Over-ADSL Encapsulation Types
437
ATM-Over-SHDSL Overview
439
Configuring ATM Mode for SHDSL Overview
439
Configuring ATM Mode on the PIM
439
Configuring ATM-Over-SHDSL Interfaces
439
Configuring Encapsulation on the ATM Physical Interface
439
Configuring SHDSL Operating Mode on an ATM Physical Interface
439
Example: Configuring an ATM-Over-SHDSL Interface
439
Verifying an ATM-Over-SHDSL Interface Configuration
439
Configuring Frame Relay
447
Chapter 16
449
Configuring Frame Relay Interface Encapsulation
449
Configuring the Frame Relay Encapsulation on a Physical Interface
450
Table 33: PIC Support for Enhanced Frame Relay Encapsulation Types
451
Example: Configuring the Encapsulation on a Physical Interface
452
Configuring the Frame Relay Encapsulation on a Logical Interface
453
Frame Relay Overview
449
Configuring Frame Relay Control Bit Translation
453
Configuring the Media MTU on Frame Relay Interfaces
454
Configuring Frame Relay Keepalives
455
Configuring Tunable Keepalives for Frame Relay LMI
456
Setting the Protocol MTU with Frame Relay Encapsulation
455
Configuring Inverse Frame Relay ARP
457
Configuring Frame Relay Dlcis
458
Configuring a Point-To-Point Frame Relay Connection
458
Configuring a Point-To-Multipoint Frame Relay Connection
458
Configuring a Multicast-Capable Frame Relay Connection
459
Configuring the Router as a DCE with Frame Relay Encapsulation
458
Configuring Channelized OC48/STM16 IQE Interfaces
461
Channelized E1 and T1 PIM Properties
463
Channelized Interface Capabilities
463
Channelized Interfaces
463
Channelized Interfaces Overview
463
Channelized IQ and IQE Interfaces Properties
463
Configuring Channelized Interfaces
461
Chapter 17 Channelized Interfaces
463
Clock Sources on Channelized Interfaces
463
Data-Link Connection Identifiers on Channelized Interfaces
463
Structure of Channelized IQ and Channelized IQE Pics
463
Table 34: Frame Relay DLCI Limitations for Channelized Interfaces
466
Table 35: Per Unit Scheduler DLCI Limitations for Channelized
467
Table 36: Protocol Family Combinations
467
Table 37: Clocking Capabilities by Channelized PIC Type
469
Figure 21: Channelized OC48/STM16 IQE PIC (in SONET Mode)
474
Figure 22: Channelized OC48/STM16 IQE PIC (in SDH Mode)
474
Figure 23: Channelized OC12 IQ PIC and Channelized OC12/STM4 IQE PIC
475
Figure 24: Channelized OC12/STM4 IQE PIC (in SDH Mode)
475
Figure 25: Channelized OC12/STM4 IQ PIC (in SDH Mode)
476
Figure 26: Channelized OC3 Ports (in SONET Mode) on Channelized OC3 IQ
476
Figure 27: Channelized CSTM1 Ports (in SDH Mode) on Channelized
477
Figure 28: Channelized STM1 IQ PIC
477
Figure 29: Channelized CDS3/E3 IQE PIC (in DS3 Mode)
478
Figure 30: Channelized CDS3/E3 IQE PIC (in E3 Mode)
478
Figure 31: Channelized DS3 IQ PIC
478
Figure 32: Channelized T1 IQ and IQE PIC
478
Figure 33: Channelized E1 IQ and IQE PIC
479
Table 38: Structural Differences: Channelized IQE Pics
480
Table 39: Structural Differences: Channelized IQ Pics
481
Table 40: Structural Differences: Channelized Pics
482
Channelized OC48/STM16 IQE Interfaces Overview
483
Figure 34: Sample Channelization of OC48/STM16 IQE PIC
483
Figure 35: Sample Channelization of OC48/STM16 IQE PIC (SDH Mode)
484
Configuring Channelized OC48/STM16 IQE Interfaces in SONET Mode
485
Configuring OC12 Interfaces
485
Configuring OC3 Interfaces
485
Figure 36: Sample Channelization of OC48/STM16 IQE PIC to E3
485
Example: Configuring OC12 Interfaces
486
Configuring OC3 Interfaces
486
Example: Configuring OC3 Interfaces
487
Configuring T3 Interfaces
487
Example: Configuring T3 Interfaces
488
Configuring T1 Interfaces
488
Example: Configuring T1 Interfaces
489
Figure 37: T1 Interfaces on a Channelized OC48 PIC
489
Configuring Fractional T1 Interfaces
490
Example: Configuring Fractional T1 Interfaces
490
Configuring Nxds0 Interfaces
491
Example: Configuring Nxds0 Interfaces
492
Figure 38: Sample Channelization of OC48 IQE PIC
492
Configuring Channelized OC48/STM16 IQE Interfaces (SDH Mode)
493
Configuring a Channelized OC48/STM16 IQE PIC for SDH Mode
493
Configuring Clear Channel STM1 and STM4 Interfaces
493
Configuring Channelized AU-4 Interfaces
493
Example: Configuring Channelized AU-4 Interfaces
494
Configuring E3 Interfaces
495
Example: Configuring E3 Interfaces
495
Configuring E1 or Channelized E1 Interfaces
496
Example: Configuring E1 and Channelized E1 Interfaces
496
Configuring Nxds0 IQE Interfaces
496
Example: Configuring Nxds0 IQE Interfaces
497
Configuring T3 or Channelized T3 Interfaces
497
Example: Configuring T3 or Channelized T3 Interfaces
497
Configuring T1 or Channelized T1 Interfaces
498
Example: Configuring T1 or Channelized T1 Interfaces
498
Configuring Link PIC Failover on Channelized OC48/STM16 IQE Interfaces
498
Example: Configuring Channelized OC48 Interfaces with Partitioned Channels
499
Channelization of OC12 PIC (SONET Mode)
501
Channelization of OC12/STM4 IQ and Channelized OC12/STM4 IQE Pics (SONET Mode)
501
Channelization of OC12/STM4 IQ PIC (SDH Mode)
501
Channelization of OC12/STM4 IQE PIC (SDH Mode)
501
Channelized OC12/STM4 IQ and IQE Interfaces Overview
501
Configuring Channelized OC12/STM4 Interfaces
501
Configuring Channelized OC12/STM4 IQ and IQE Interfaces
501
Mode)
501
Configuring Channelized OC12/STM4 IQE Interfaces (SDH Mode)
501
Figure 39: Sample Channelization of OC12/STM4 IQ or IQE PIC
502
Figure 40: Sample Channelization of OC12/STM4 IQE PIC (SDH Mode)
503
Figure 41: Sample Channelization of OC12/STM4 IQ PIC (SDH Mode)
504
Configuring an OC12/STM4 Interface
505
Configuring T3 Interfaces
505
Figure 42: Sample Channelization of OC12 PIC (Non IQ and IQE)
505
Example: Configuring T3 Interfaces
507
Figure 43: T1 Interfaces on a Channelized OC12 PIC
509
Figure 44: Sample Channelization of OC12 IQE PIC
511
Configuring an Unpartitioned SDH (VC-4-4C) Interface on a Channelized
513
Oc12/Stm4 Iqe Pic
513
Example: Configuring an Unpartitioned SDH (VC-4-4C) Interface
514
Configuring Channelized OC12/STM4 IQE Pics for SDH Mode
513
Configuring SDH (VC-4) Interfaces on Channelized OC12/STM4 IQE Pics
514
Example: Configuring SDH (VC-4) Interfaces
515
Configuring Channelized AU-4 Interfaces
515
Example: Configuring Channelized AU-4 Interfaces
515
Configuring E3 Interfaces
516
Example: Configuring E3 Interfaces
516
Configuring E1 or Channelized E1 Interfaces
517
Example: Configuring E1 or Channelized CE1 Interfaces
517
Configuring Nxds0 Interfaces on Channelized OC12/STM4 IQE Pics
517
Example: Configuring Nxds0 Interfaces
518
Configuring an Unpartitioned SDH (VC-4-4C) Interface on a Channelized
518
Oc12/Stm4 Iq Pic
518
Example: Configuring an Unpartitioned SDH (VC-4-4C) Interface
519
Configuring Channelized OC12/STM4 IQ Pics for SDH Mode
518
Configuring SDH (VC-4) Interfaces on Channelized OC12/STM4 IQ Pics
519
Example: Configuring SDH (VC-4) Interfaces
520
Configuring Channelized AU-4 Interfaces
520
Example: Configuring Channelized AU-4 Interfaces
521
Configuring T3 or Channelized T3 Interfaces under Channelized AU-4 Interfaces
521
Example: Configuring T3 or Channelized T3 Interfaces
521
Configuring T1 or Channelized T1 Interfaces under Channelized AU-4 Interfaces
522
Channelized AU-4 Interfaces
522
Configuring T1 or Channelized T1 Interfaces under Channelized T3 Interfaces
522
Example: Configuring T1 or Channelized T1 Interfaces under Channelized T3 Interfaces
523
Configuring Nxds0 Interfaces on Channelized OC12/STM4 IQ Pics
523
Example: Configuring Nxds0 Interfaces
523
Configuring Channelized OC12 Interfaces
524
Table 41: OC12-To-DS3 Numbering Scheme
524
Example: Configuring Channelized OC12 Interfaces
525
Configuring Link PIC Failover on Channelized OC12/STM4 IQ and IQE Interfaces
526
Example: Configuring a Channelized OC12 IQ Interface as an Unpartitioned Clear Channel
527
Example: Configuring Channelized OC12 Interfaces with Partitioned Channels
530
Channelized OC3 IQ and IQE Overview
533
Configuring a Clear Channel on Channelized OC3 IQ and IQE Pics
533
Configuring Channelized OC3 IQ and IQE Interfaces
533
Configuring T3 Interfaces on IQ and IQE Interfaces
533
Figure 45: Channelized OC3 IQ Interface Example for Show Interfaces
534
Example: Configuring T3 Interfaces
536
Partitions, OC Slices, Interface Types, and Time Slots
533
Configuring T1 and Nxds0 Interfaces
536
Example: Configuring T1 and Nxds0 Interfaces
538
Figure 46: T1 Interfaces on a Channelized OC3 PIC
538
Figure 47: Sample Channelization of OC3 IQ or IQE PIC
538
Example: Setting Remote Loopback and Running BERT Tests on Nxds0 Interfaces
539
Configuring Fractional T1 IQ Interfaces
540
Example: Configuring Fractional T1 IQ Interfaces
540
Configuring Link PIC Failover on Channelized OC3 IQ and IQE Interfaces
540
Channelized STM1 Interfaces Overview
543
Configuring Channelized STM1 Interfaces
543
Configuring Channelized STM1 IQ and IQE Interfaces
543
Configuring an STM1 IQ or STM1 IQE Interface
543
Configuring E1 IQ and IQE Interfaces
543
Example: Configuring E1 IQ and IQE Interfaces
544
Configuring Fractional E1 IQ and IQE Interfaces
545
Example: Configuring Fractional E1 Interfaces
546
Configuring an Nxds0 IQ Interface
546
Example: Configuring an Nxds0 IQ Interface
547
Example: Configuring Channelized STM1 IQ and IQE Interfaces
547
Configuring Channelized STM1 Interfaces
549
Configuring Channelized STM1 Interface Properties
549
Configuring Virtual Tributary Mapping of Channelized STM1 Interfaces
550
Table 42: Channelized STM1-To-E1 Channel Mapping
551
Table 43: Channelized STM1-To-T1 Channel Mapping
553
Configuring Link PIC Failover on Channelized STM1 Interfaces
556
Example: Configuring Channelized STM1 Interfaces
557
Configuring Channelized T3 Interfaces
559
Configuring Channelized T3 IQ Interfaces
559
Configuring T3 IQ Interfaces
559
Configuring T1 IQ Interfaces
559
Example: Configuring T1 IQ and IQE Interfaces
560
Configuring Fractional T1 IQ and IQE Interfaces
560
Example: Configuring Fractional T1 IQ Interfaces
561
Configuring an Nxds0 IQ Interface
561
Example: Configuring an Nxds0 IQ Interface
562
Configuring Channelized DS3-To-DS0 Interfaces
562
Table 44: Ranges for Channelized DS3-To-DS0 Configuration
563
Configuring Channelized DS3-To-DS1 Interfaces
565
Example: Configuring Channelized T3 IQ Interfaces
566
Examples: Configuring Channelized DS3-To-DS0 Interfaces
567
Figure 48: Sample Channelization of DS3 IQ or IQE PIC
567
Examples: Configuring Channelized DS3-To-DS1 Interfaces
570
Channelized T1 IQ and IQE Interfaces Overview
575
Configuring Channelized T1 Interfaces
575
Configuring Channelized T1 IQ and IQE Interfaces
575
Configuring T1 IQ and IQE Interfaces
575
Configuring Fractional T1 IQ and IQE Interfaces
575
Example: Configuring Fractional T1 IQ and IQE Interfaces
576
Configuring Nxds0 IQ and IQE Interfaces
577
Example: Configuring an Nxds0 IQ or IQE Interface
577
Configuring Payload Loopback
577
Table 45: Ranges for Channelized T1 IQ Configuration
578
Configuring Channelized T1 Interface Properties
579
Example: Configuring Channelized T1 IQ and IQE Interfaces
579
Channelized E1 IQ and IQE Interfaces Overview
581
Configuring Channelized E1 Interfaces
581
Configuring Channelized E1 IQ and IQE Interfaces
581
Configuring E1 IQ and IQE Interfaces
581
Configuring Fractional E1 IQ and IQE Interfaces
581
Example: Configuring Fractional E1 IQ and IQE Interfaces
582
Configuring Nxds0 IQ and IQE Interfaces
582
Example: Configuring an Nxds0 IQ or IQE Interface
583
Configuring Channelized E1 Interfaces
583
Table 46: Ranges for Channelized E1 Configuration
584
Configuring Channelized E1 Interface Properties
585
Example: Configuring Channelized E1 IQ or IQE Interfaces
585
Example: Configuring Channelized E1 Interfaces
586
Allocating B-Channels for Dialout
589
Channelized E1 PRI and T1 PRI Overview
589
Chapter 25 Configuring Channelized E1 PRI and T1 PRI Interfaces
589
Interface
590
Part 8 Configuring Circuit Emulation Pics
597
Configuring a Channelized T1/E1 Interface to Drop and Insert Time Slots
589
Configuring a Clear Channel on a Dual-Port Channelized T1-E1 PIM
589
Configuring PRI Interfaces
589
Configuring Primary Rate Interfaces
589
Example: Configuring a Channelized T1 Interface as Primary Rate
589
Circuit Emulation Pics Overview
599
Displaying Information about Circuit Emulation Pics
599
Mobile Backhaul and Circuit Emulation Overview
599
Mobile Backhaul Application Overview
599
Understanding Circuit Emulation PIC Clocking Features
599
Understanding Circuit Emulation PIC Types
599
Understanding T1 and E1 Options Exceptions on Circuit Emulation Pics
599
Figure 49: Mobile Backhaul Application
600
Configuring Satop Emulation on T1/E1 Interfaces on Circuit Emulation
603
Pics
603
Setting the Emulation Mode
605
Configuring Satop Emulation on T1/E1 Interfaces
605
Setting the Encapsulation Mode
606
Setting the Satop Options
606
T1 FDL Support
606
T1/E1 Loopback Support
606
Pseudowire Interface Configuration
607
Configuring Satop on 4-Port Channelized OC3/STM1 Circuit Emulation Pics
603
Configuring SONET/SDH Framing Mode at the PIC Level
603
Configuring SONET/SDH Framing Mode at the Port Level
603
Configuring COC3 Ports down to T1 Channels
603
Configuring CSTM1 Ports down to E1 Channels
603
Configuring Satop Support on Circuit Emulation Pics
603
ATM Support on Circuit Emulation Pics Overview
609
Configuring ATM Support on Circuit Emulation Pics
609
Configuring the 12-Port Channelized T1/E1 Circuit Emulation PIC Operating Mode
609
T1/E1 Mode Selection
611
12-Port Channelized T1/E1 Circuit Emulation PIC Configuration Statements
611
Figure 50: 12-Port T1/E1 Circuit Emulation PIC Possible Interfaces
611
Figure 51: 12-Port T1/E1 Circuit Emulation PIC Possible Interfaces
611
Configuring the 4-Port Channelized COC3/STM1 Circuit Emulation PIC Operating Mode
612
T1/E1 Mode Selection
612
Figure 52: 4-Port Channelized COC3/STM1 Circuit Emulation PIC Possible
613
Figure 53: 4-Port Channelized COC3/STM1 Circuit Emulation PIC Possible Interfaces (E1 Size)
613
Configuring a Port for SONET or SDH Mode on a 4-Port Channelized COC3/STM1 Circuit Emulation PIC
614
Configuring an ATM Interface on a COC1
614
ATM IMA Configuration Overview
615
IMA Version
615
IMA Groups
615
Group Frame Size
615
IMA Clock Mode
615
IMA Group Symmetry
615
Minimum Active Links
615
State Transition Variables: Alpha, Beta, and Gamma
615
IMA Link Addition and Deletion
615
IMA Test Pattern Procedure
615
Table 47: IMA Frame Synchronization Link State Transition Variables
617
Table 48: IMA Group Alarms with IMA Standard Requirement Numbers
617
Table 49: IMA Group Defects with IMA Standard Requirement Numbers
618
Table 50: IMA Link Alarms with IMA Standard Requirement Numbers
618
Table 51: IMA Link Defects with IMA Standard Requirement Numbers
619
Table 52: IMA Link Statistics with IMA Standard Requirement Numbers
620
IMA Clocking
621
Configuring ATM IMA
621
Creating the IMA Groups (ATM Interfaces)
621
Linking Constituents to Form Group and T1/E1 Options
621
ATM Options and Encapsulations and Families
621
IMA Link Options
621
IMA Group Options
621
Configuring ATM Pseudowires
623
Cell Relay Mode (Atm-L2Circuit-Mode Cell)
623
Configuring VP or Port Promiscuous Mode
623
Configuring AAL5 SDU Mode (Atm-L2Circuit-Mode Aal5)
623
Atm Oam
625
VP Pseudowires (CCC Encapsulation)
625
Port Pseudowires (CCC Encapsulation)
625
VC Pseudowires (CCC Encapsulation)
625
Scaling
625
Configuring Layer 2 Circuit and Layer 2 VPN Pseudowires
626
Configuring the PIC Type
626
Congestion Control
626
Qos/Shaping
626
Supported Interface Configurations
626
ATM Limitations
627
Part 9 Configuring E1, E3, T1, and T3 Interfaces
629
Chapter 29 Configuring E1 Interfaces
631
Configuring E1 BERT Properties
631
Configuring E1 Data Inversion
631
Example: Configuring E1 Loopback Capability
635
Figure 54: Remote and Local E1 Loopback
635
Configuring E1 Physical Interface Properties
631
Configuring the E1 Frame Checksum
631
Configuring the E1 Idle Cycle Flag
631
E1 Interfaces Overview
631
Configuring E1 Start and End Flags
636
Configuring Fractional E1 Time Slots
636
Example: Configuring Fractional E1 Time Slots
637
Chapter 30 Configuring E3 Interfaces
639
Configuring E3 BERT Properties
639
Configuring E3 Data Inversion
639
Configuring E3 Loopback Capability
639
Table 53: Subrate Values for E3 Digital Link Compatibility Mode
642
Example: Configuring E3 Loopback Capability
644
Figure 55: Remote and Local E3 Loopback
644
Configuring E3 Physical Interface Properties
639
Configuring the E3 CSU Compatibility Mode
639
Configuring the E3 Frame Checksum
639
Configuring the E3 Idle Cycle Flag
639
E3 Interfaces Overview
639
Configuring E3 HDLC Payload Scrambling
645
Configuring the E3 Start and End Flags
645
Configuring E3 IQ and IQE Unframed Mode
646
Chapter 31 Configuring T1 Interfaces
647
Configuring T1 BERT Properties
647
Configuring T1 Byte Encoding
647
Configuring T1 CRC Error Major Alarm Thresholds
647
Configuring T1 CRC Error Minor Alarm Thresholds
647
Configuring T1 Data Inversion
647
Configuring T1 Physical Interface Properties
647
Configuring the T1 Buildout
647
T1 Interfaces Overview
647
Configuring T1 Framing
652
Configuring T1 Line Encoding
652
Configuring the T1 Remote Loopback Response
652
Configuring T1 Loopback Capability
653
Figure 56: Remote and Local T1 Loopback
653
Configuring the T1 Idle Cycle Flag
654
Configuring Fractional T1 Time Slots
655
Example: Configuring Fractional T1 Time Slots
655
Configuring T1 Start and End Flags
655
Chapter 32 Configuring T3 Interfaces
657
Configuring T3 BERT Properties
657
Configuring T3 Physical Interface Properties
657
T3 Interfaces Overview
657
Disabling T3 C-Bit Parity Mode
659
Configuring the T3 CSU Compatibility Mode
660
Table 54: Subrate Values for T3 Digital Link Compatibility Mode
661
Configuring the T3 Frame Checksum
662
Configuring the T3 FEAC Response
663
Configuring the T3 Idle Cycle Flag
663
Configuring the T3 Line Buildout
663
Configuring T3 Loopback Capability
664
Configuring the Channelized T3 Loop Timing
664
Figure 57: Remote and Local T3 Loopback
665
Configuring T3 HDLC Payload Scrambling
666
Configuring T3 Start and End Flags
667
Examples: Configuring T3 Interfaces
667
Part 10 Configuring Ethernet Interfaces
671
Configuring Ethernet Interfaces
671
Chapter 33 Configuring Ethernet Interfaces
673
Example: Configuring J Series Services Router Switching Interfaces
679
Configuring Ethernet Physical Interface Properties
673
Configuring J Series Services Router Switching Interfaces
673
Ethernet Interfaces Overview
673
MX Series Router Interface Identifiers
679
Enabling Ethernet MAC Address Filtering
680
Filtering Specific MAC Addresses
681
Configuring Ethernet Loopback Capability
682
Configuring Flow Control
683
Configuring the Link Characteristics on Ethernet Interfaces
683
Ignoring Layer 3 Incomplete Errors
683
Configuring Gratuitous ARP
684
Adjusting the ARP Aging Timer
685
Configuring the Ingress Rate Limit
686
Configuring the Interface Speed on Ethernet Interfaces
686
Configuring Weighted Random Early Detection
686
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Juniper JUNOS 10.1 - S REV 4 Release Note (205 pages)
Brand:
Juniper
| Category:
Software
| Size: 1.51 MB
Table of Contents
Table of Contents
1
Release Notes
1
JUNOS Software Release Notes for Juniper Networks M Series Multiservice Edge Routers, MX Series Ethernet Service Routers, and T Series Core Routers
6
Class of Service
6
High Availability
12
Interfaces and Chassis
12
JUNOS XML API and Scripting
18
MPLS Applications
21
Multiplay
22
Routing Policy and Firewall Filters
23
Routing Protocols
24
Services Applications
27
Subscriber Access Management
27
System Logging
36
User Interface and Configuration
38
Changes in Default Behavior and Syntax in JUNOS Release 10.1 for M Series, MX Series, and T Series Routers
42
Class of Service
42
Forwarding and Sampling
42
Interfaces and Chassis
42
Layer 2 Ethernet Services
46
MPLS Applications
46
Multiplay
47
Routing Policy and Firewall Filters
47
Routing Protocols
47
Services Applications
48
Subscriber Access Management
50
User Interface and Configuration
51
Vpns
52
Issues in JUNOS Release 10.1 for M Series, MX Series, and T Series Routers
54
Current Software Release
54
Previous Releases
73
Errata and Changes in Documentation for JUNOS Software Release 10.1 for M Series, MX Series, and T Series Routers
94
Changes to the JUNOS Documentation Set
94
Errata
94
Upgrade and Downgrade Instructions for JUNOS Release 10.1 for M Series, MX Series, and T Series Routers
98
Basic Procedure for Upgrading to Release 10.1
98
Upgrading a Router with Redundant Routing Engines
101
Upgrading Juniper Routers Running Draft-Rosen Multicast VPN to JUNOS Release 10.1
101
Upgrading the Software for a Routing Matrix
103
Upgrading Using ISSU
104
Upgrading from JUNOS Release 9.2 or Earlier on a Router Enabled for both PIM and NSR
104
Downgrade from Release 10.1
105
JUNOS Software Release Notes for Juniper Networks SRX Series Services
107
Gateways and J Series Services Routers
107
New Features in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
107
Software Features
108
Hardware Features
122
Changes in Default Behavior and Syntax in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
123
Application Layer Gateways (Algs)
123
Chassis Cluster
124
Command-Line Interface (CLI)
125
Configuration
127
Flow and Processing
128
Interfaces and Routing
129
Intrusion Detection and Prevention (IDP)
129
J-Web
130
Management and Administration
130
Security
131
Wlan
131
Known Limitations in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
132
[Accounting-Options] Hierarchy
132
AX411 Access Point
132
Chassis Cluster
132
Command-Line Interface (CLI)
133
Dynamic VPN
134
Flow and Processing
134
Hardware
135
Interfaces and Routing
136
Intrusion Detection and Prevention (IDP)
138
J-Web
139
Netscreen-Remote
140
Network Address Translation (NAT)
140
Performance
141
Snmp
141
System
141
Unified Threat Management (UTM)
141
Vpns
141
Wlan
141
Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
142
Outstanding Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
142
Resolved Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
162
Errata and Changes in Documentation for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
165
Application Layer Gateways (Algs)
165
Attack Detection and Prevention
165
CLI Reference
166
Command-Line Interface (CLI)
166
Compactflash Card Support
166
Flow and Processing
166
Hardware Documentation
167
Installing Software Packages
168
Integrated Convergence Services
169
Interfaces and Routing
169
Intrusion Detection and Prevention (IDP)
170
J-Web
172
Screens
172
Hardware Requirements for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
172
Transceiver Compatibility for SRX Series and J Series Devices
173
Power and Heat Dissipation Requirements for J Series Pims
173
Supported Third-Party Hardware for J Series Services Routers
173
J Series Compactflash and Memory Requirements
174
Dual-Root Partitioning Scheme Documentation for SRX Series Services Gateways
175
Dual-Root Partitioning Scheme
175
Maximizing ALG Sessions
183
Using Dual Chassis Cluster Control Links: Upgrade Instructions for the Second Routing Engine
184
Upgrade and Downgrade Instructions for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
185
Juniper JUNOS 10.1 - S REV 4 Release Note (204 pages)
Brand:
Juniper
| Category:
Software
| Size: 1.48 MB
Table of Contents
Table of Contents
1
JUNOS Software Release Notes for Juniper Networks M Series Multiservice Edge Routers, MX Series Ethernet Service Routers, and T Series Core Routers
6
Class of Service
6
High Availability
12
Interfaces and Chassis
12
JUNOS XML API and Scripting
18
MPLS Applications
21
Multiplay
22
Routing Policy and Firewall Filters
23
Routing Protocols
24
Services Applications
27
Subscriber Access Management
27
System Logging
36
User Interface and Configuration
38
Changes in Default Behavior and Syntax in JUNOS Release 10.1 for M Series, MX Series, and T Series Routers
42
Class of Service
42
Forwarding and Sampling
42
Interfaces and Chassis
42
Layer 2 Ethernet Services
46
MPLS Applications
46
Multiplay
47
Routing Policy and Firewall Filters
47
Routing Protocols
47
Services Applications
48
Subscriber Access Management
50
User Interface and Configuration
51
Vpns
52
Issues in JUNOS Release 10.1 for M Series, MX Series, and T Series Routers
54
Current Software Release
54
Previous Releases
73
Errata and Changes in Documentation for JUNOS Software Release 10.1 for M Series, MX Series, and T Series Routers
86
Changes to the JUNOS Documentation Set
86
Errata
86
Upgrade and Downgrade Instructions for JUNOS Release 10.1 for M
86
Series, MX Series, and T Series Routers
89
Basic Procedure for Upgrading to Release 10.1
90
Upgrading a Router with Redundant Routing Engines
92
Upgrading Juniper Routers Running Draft-Rosen Multicast VPN to JUNOS Release 10.1
92
Upgrading the Software for a Routing Matrix
94
Upgrading Using ISSU
95
Upgrading from JUNOS Release 9.2 or Earlier on a Router Enabled for both PIM and NSR
95
Downgrade from Release 10.1
96
JUNOS Software Release Notes for Juniper Networks SRX Series Services Gateways and J Series Services Routers
98
New Features in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
98
Software Features
99
Hardware Features
117
Changes in Default Behavior and Syntax in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
117
Application Layer Gateways (Algs)
118
Chassis Cluster
118
Command-Line Interface (CLI)
119
Configuration
122
Flow and Processing
123
Interfaces and Routing
124
Intrusion Detection and Prevention (IDP)
124
J-Web
125
Management and Administration
125
Security
126
Known Limitations in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
126
[Accounting-Options] Hierarchy
126
AX411 Access Point
126
Chassis Cluster
126
Command-Line Interface (CLI)
128
Dynamic VPN
128
Flow and Processing
129
Hardware
129
Interfaces and Routing
130
Intrusion Detection and Prevention (IDP)
133
J-Web
134
Netscreen-Remote
135
Network Address Translation (NAT)
135
Performance
136
Snmp
136
System
136
Unified Threat Management (UTM)
136
Vpns
136
Wlan
136
Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
137
Outstanding Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
137
Resolved Issues in JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
158
Errata and Changes in Documentation for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
163
Application Layer Gateways (Algs)
163
Attack Detection and Prevention
163
CLI Reference
164
Command-Line Interface (CLI)
164
Compactflash Card Support
164
Flow and Processing
164
Hardware Documentation
165
Installing Software Packages
166
Integrated Convergence Services
167
Interfaces and Routing
167
Intrusion Detection and Prevention (IDP)
168
J-Web
170
Screens
170
Hardware Requirements for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
170
Transceiver Compatibility for SRX Series and J Series Devices
171
Power and Heat Dissipation Requirements for J Series Pims
171
Supported Third-Party Hardware for J Series Services Routers
171
J Series Compactflash and Memory Requirements
172
Dual-Root Partitioning Scheme Documentation for SRX Series Services Gateways
173
Dual-Root Partitioning Scheme
173
Maximizing ALG Sessions
181
Using Dual Chassis Cluster Control Links: Upgrade Instructions for the Second Routing Engine
182
Upgrade and Downgrade Instructions for JUNOS Release 10.1 for SRX Series Services Gateways and J Series Services Routers
183
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