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4.1 74LCX373APW-X (IC512,IC513) : Octal D-type latch
• Pin layout
OE
1
Q0
2
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10
(TOP VIEW)
• Pin function
Symbol
Description
D0~D7
Data inputs
LE
Latch enable input
OE
Output enable input
Q0~Q7
3-State latch outputs
SECTION 4
Description of major ICs
20
VCC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
11
LE
• Truth table
INPUTS
LE
OE
X
H
H
L
H
L
L
L
H = HIGH Voltage level
L = LOW Voltage level
Z = High impedance
X = Immaterial
Q0 = Previous Q0 before HIGH to LOW transition of latch enable
• Block diagram
D0
D1
D2
D3
3
4
7
8
D
D
D
Q
Q
Q
L
L
L
11
LE
1
OE
2
5
6
Q0
Q1
Q2
XV-N40BK,XV-N44SL
OUTPUT
Dn
Qn
X
Z
L
L
H
H
X
Q0
D4
D5
D6
D7
13
14
17
18
D
D
D
D
D
Q
Q
Q
Q
L
L
L
L
9
12
15
16
Q3
Q4
Q5
Q6
(No.A0040)1-23
Q
L
19
Q7
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