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GP3 Backend block diagram (LW98 PG)
VLCD_POWER
+1.26V_URSA5
DC-DC Converter
DC-DC Converter
DC-DC Converter
(AOZ1073AI)
(AOZ1073AI)
(AOZ1073AI)
SPI FLASH
SPI FLASH
SPI FLASH
(4Mbit)
(4Mbit)
(4Mbit)
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
-
-
-
1Gbit (x16)
1Gbit (x16)
1Gbit (x16)
-
-
800Mbps
800Mbps
- 800Mbps
+3.3_URSA5
DC-DC Converter
DC-DC Converter
+1.5V_DDR
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
(AOZ1072AI)
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Xin/
Xout
SPI_DI
SPI_DO/CK/CS
URSA5
(0xB4, master)
DDR0_A[12:0]/
BA[2:0]/CLK/CKE
GPIO
DDR0_DATA[15:
/XOUT
0]
I2C_M
Quad-link LVDS
Dual-link HF mini-LVDS
(@297MHz)
VCC_LCM/VDD_LCM/
HVDD
P-GAMMA
P-GAMMA
I2C_SC
P-GAMMA
IC
IC
IC
L
(BUF08630)
(BUF08630)
I2C_SDA
(BUF08630)
(0xE8)
(0xE8)
(0xE8)
80P mini-LVDS Output
RIGHT
51Pin LVDS Input
VLCD_POWER
(+12V)
Dual-link LVDS(@74.25MHz)
M/SPIF
XTAL_IN
XTAL_OUT
X-Tal
(24Mhz)
DDR1_A[12:0]/
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
BA[2:0]/CLK/CKE
-
-
-
1Gbit (x16)
1Gbit (x16)
1Gbit (x16)
DDR1_DATA[15:
-
-
800Mbps
800Mbps
- 800Mbps
0]
Quad-link LVDS
XTR
I2C_SCL
I2C_TCON_SCL
T-Con
I2C_SDA
I2C_TCON_SDA
(0x72)
Dual-link HF mini-LVDS
VCC_LCM/VDD_LCM/
HVDD
GMA[18:15],
GMA[9:5]
I2C_SC
P_VCOM
L
(BUF08630)
(BUF08630)
I2C_SDA
(BUF08630)
Z_OUT
VLCD_POWER
DC-DC Converter
DC-DC Converter
DC-DC Converter
URSA5
I2C_SCL_M
I2C_S
(0xB8, slave)
I2C_SDA_M
XIN
VLCD_POWER
I2C_SC
L
(MAX17139)
(MAX17139)
EEPROM
EEPROM
(MAX17139)
EEPROM
I2C_SDA
(0x42)
(0x42)
(64kbit)
(64kbit)
(64kbit)
(@297MHz)
GMA[14:10],
GMA[4:1]
P-GAMMA
P-GAMMA
P-GAMMA
IC
IC
IC
(0xEA)
(0xEA)
(0xEA)
80P mini-LVDS Output
LEFT
+3.3V_URSA5
(AOZ1073AI)
(AOZ1073AI)
(AOZ1073AI)
VCC_LCM/VDD_LCM
/
PMIC
PMIC
PMIC
VGH/VGL/HVDD/VCORE
(0x42)
LGE Internal Use Only
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