Sony CDX-C880 Service Manual page 33

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Pin No.
52
53
54
55
56
57
58
59
60
61
62
63
64
65, 66
67
68
69
70
71
72
73
74
75
76
TE
L 13942296513
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
www
100
101
102
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103
104
105
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Pin Name I/O
ASY.I I Asymmetry comparate voltage input
ASY.O O EFM full-swing output ("L" : VSS, "H" : VDD)
VC I Center voltage input
FE I Focus error signal input
SE I Sled error signal input
TE I Tracking error signal input
CE I Center error signal input
RFDC I RF signal input
RFC I Condenser connection pin for LPF time constant of RF signal.
ADIO O OP amplifier output (Not used.)
AVSS3 — Analog GND
IGEN I Current source reference resistor connection for OP amplifier.
AVDD3 — Analog power supply
TES2, 3 I TEST pin (Fixed at "L".)
VSS2 — Digital GND
TEST I TEST pin (Fixed at "L".)
SFDR O Sled drive output
SRDR O Sled drive output
TFDR O Tracking drive output
TRDR O Tracking drive output
FFDR O Focus drive output
FRDR O Focus drive output
VDD2 — Digital power supply
COUT O Track number count signal output (Not used.)
LOCK O Not used.
MDS O Servo control output of spindle motor. (Not used.)
MDP O Servo control output of spindle motor.
SSTP I Disc most inner track detection signal input
FSTO O 2/3 frequency division output of pins 103 and 104.
FSTI I Reference clock input for digital servo.
XTSL I X'tal select input ("L" : 16.9344 MHz)
C4M O 4.2336 MHz output
WDCK O D/A interface. Word clock f = 2Fs
VDD3 — Digital power supply
LRCK O D/A interface. LR clock f = Fs
LRCKI I LR clock input to DAC. (48 bit slot) (Not used.)
PCMD O D/A interface. Serial data (2's COMP, MSB first)
PCMDI I Audio data input to DAC. (48 bit slot) (Not used.)
BCK O D/A interface. Bit clock
BCKI I Bit clock input to DAC. (48 bit slot) (Not used.)
EMPH O Not used.
EMPHI I De-emphasis ON/OFF of DAC. ("H" : ON, "L" : OFF) (Not used.)
VSS3 — Digital GND
AVSS1 — L-ch, Analog GND.
AVDD1 — L-ch, Analog power supply.
AOUT1 O L-ch, Analog output. (Not used.)
AIN1 I L-ch, OP amplifier input. (Not used.)
LOUT1 O L-ch, LINE output. (Not used.)
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y
AVSS1 — L-ch, Analog GND.
XVDD — Analog power supply for master clock.
i
XTAI I X'tal oscillator input of master clock (16.9344 MHz).
XTAO O X'tal oscillator output of master clock. (Not used.)
XVSS — Analog GND for master clock. (Not used.)
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Pin Description
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