Sony STR-V333ES Service Manual page 48

IC1304, 1305 CXD2712R AUDIO DSP MEMORY CONTROL (DIGITAL BOARD)
Pin No. Pin Name
1 VSS3
SOA to SOD
2 to 5
6, 7 ECJ0, ECJ1
8 NC
XHDWR
9
10 XHDRD
11 VSS4
12 VDD2
13 HRDY
14 XHDCS
15 HA0
16 to 20 HD0 to HD4
VSS5
21
22 VDD3
23 to 25 HD5 to HD7
26 XRST
27 to 30 FGP0 toFGP3
31 VSS6
32 to 40 ED0 to ED8
41 VSS7
VDD4
42
43 to 49 ED9 to ED15
50 TSTD
VSS8
51
52 VDD5
53 to 60 ED16 to ED23
61 VSS9
ED24 to ED31
62 to 69
70 XOE
71 VSS10
72 VDD6
73 CAS
74 XWE
75 RAS
76 to 80 EA0 to EA4
81 VSS11
82 VDD7
83 to 89 EA to EA11
EA12
90
91 VSS0
92 to 95 EA13 to EA16
96 TSTA
97 PLDIVF
98 PLDIVB
99 CLKI
100 CLKO
48
Description
I/O
— Ground terminal
Serial data output to the A/D, D/A converter
O
Conditional jump input terminal
I
O Not used (fixed at "L")
I Write data input from the system controller (IC1201)
Read data input terminal
I
Ground terminal
—
— Power supply terminal (+3.3V)
O Ready signal output to the system controller (IC1201)
Chip select signal input from the system controller (IC1201)
I
I Address signal input from the system controller (IC1201)
I/O Two-way data bus with the system controller (IC1201)
— Ground terminal
Power supply terminal (+3.3V)
—
I/O Two-way data bus with the system controller (IC1201)
I Reset signal input from the system controller (IC1201)
Data output terminal for the test
I/O
Ground terminal
—
I/O Not used (No connection)
— Ground terminal
Power supply terminal (+3.3V)
—
I/O Not used (No connection)
I Not used (Connected to ground)
— Ground terminal
Power supply terminal (+3.3V)
—
Two-way data bus with the S-RAM
I/O
— Ground terminal
Two-way data bus with the S-RAM
I/O
Output enable signal output to the S-RAM
O
— Ground terminal
— Power supply terminal (+3.3V)
External RAM column address strobe signal output terminal (Not used)
O
O External RAM write enable
O External RAM raw address strobe signal output terminal (Not used)
I/O Address signal output to the S-RAM or test data input from the S-RAM
Ground terminal
—
Power supply terminal (+3.3V)
—
I/O Address signal output to the S-RAM or test data input from the S-RAM
Address signal output to the S-RAM
O
Ground terminal
—
O Address signal output to the S-RAM
I Test data input terminal
PLL input frequency select terminal
I
PLL input frequency select terminal
O
I Master clock signal input terminal (Connecting Xtal)
O Master clock signal output terminal (Connecting Xtal)