K4S643232E (Sy: Ic717); Block Diagram; Pin Function Description - Denon DVD-3910 Service Manual

QQ
3 7 63 1515 0

K4S643232E (SY: IC717)

PIN CONFIGURATION
V 1
DD
DQ0 2
V 3
DDQ
DQ1 4
DQ2 5
V 6
SSQ
DQ3 7
DQ4 8
V 9
DDQ
DQ5 10
DQ6 11
V 12
SSQ
DQ7 13
N.C 14
V 15
DD
DQM0 16
WE 17
CAS 18
RAS 19
CS 20
N.C 21
BA0 22
BA1 23
A10/AP 24
A0 25
A1 26
A2 27
DQM2 28
V 29
DD
N.C 30
DQ16 31
V 32
SSQ
DQ17 33
DQ18 34
V 35
DDQ
DQ19 36
DQ20 37
V 38
SSQ
DQ21 39
DQ22 40
V 41
DDQ
DQ23 42
V 43
DD
TE
L 13942296513

PIN FUNCTION DESCRIPTION

Pin
CLK
System clock
CS
Chip select
CKE
Clock enable
A ~ A
0 10
Address
BA0,1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 3
Data input/output mask
DQ ~
0 31 Data input/output
V /V
www DD SS
Power supply/ground
V /V
DDQ SSQ
Data output power/ground
NC
.
No Connection
http://www.xiaoyu163.com

BLOCK DIAGRAM

V
86
SS
DQ15
85
84 V
SSQ
DQ14
83
DQ13
82
V
81
DDQ
80 DQ12
DQ11
79
V
78
SSQ
77 DQ10
76 DQ9
V
75
DDQ
DQ8 CLK
74
73 N.C
72 V
SS
ADD
DQM1
71
N.C
70
69 N.C
CLK
68
CKE
67
66 A9
65 A8
LCKE
A7
64
A6
63
62 A5
A4
61
A3
60
59 DQM3
58 V
SS
N.C
57
DQ31
56
55 V
DDQ
DQ30
54
DQ29
53
V
52
SSQ
51 DQ28
DQ27
50
V
49
DDQ
48 DQ26
DQ25
47
V
46
SSQ
DQ24
45
44 V
SS
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
x ao u163
y
immunity.
This pin is recommended to be left No connection on the device.
i
http://www.xiaoyu163.com
2 9
8
Bank Select
LRAS LCBR LWE LCAS
Timing Register
CLK CKE CS RAS CAS
Q Q
3 6 7 1 3 1 5
Input Function
~ RA , Column address : CA
0 10
after the clock and masks the output.
SHZ
co
.
66
DVD-3910
9 4 2 8
Data Input Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR LDQM
WE DQM
0 5 8 2 9 9 4 2 8
~ CA
0 7
m
9 9
LWE
LDQM
DQi
9 9