Philips for Intel Socket 775 processor Service Manual page 28

EN 28 6. S/SD/HD 3.1 PDP
42" HDv3
LOGIC CONTROL
DATA_R
8Bits
DATA_G
8Bits
DATA_B
8Bits
DCLK
Vsync
Hsync
Enable
LVDS
Interface
S37" SDv4
LOGIC CONTROL
DATA_R
8 Bits
DATA_G
8 Bits
DATA_B
8 Bits
DCLK
Vsync
Hsync
Enable
LVDS
Interface
Block Diagrams, Testpoint Overview, and Waveforms
Display
Data
Driver
Timing
Scan
Timing
- Vcc : Voltage for Logic Control
- Vdd : Voltage for Fet driver
- Va
- Vs
- Vsc : Voltage for scan pulse
- Ve
- Vset : Voltage for Y ramp pulse
DRIVER CIRCUIT & PANEL
- Vcc : Voltage for Logic Control
- Vdd : Voltage for FET driver
- Va : Voltage for address pulse
- Vs : Voltage sustain pulse
- Vsc : Voltage for scan pulse
- Ve : Voltage for X ramp pulse
- Vset : Voltage for Y ramp pulse
DRIVER CIRCUIT & PANEL
Column Driver
1024× 768 Pixels
1024× 3× 768 Cells
Column Driver
Vcc Vdd
Va Vs
Vset Vsc Ve
Reference
: Voltage for address pulse
: Voltage sustain pulse
: Voltage for X ramp pulse
852 x 480 Pixels
852 x 3 x 480 Cells
Column Driver
Reference