Sharp CD-C471H Service Manual page 57

ICT21 VHiLC72720/-1:RDS Decorder (LC72720)
Pin No. Terminal Name
1 VREF
2 MPXIN
3 Vdda
4 Vssa
5 FLOUT
6 CIN
7 T1
8 T2
9* T3 (RDCL)
10* T4 (RDDA)
11 * T5 (RSFT)
12 XOUT
13 XIN
14 Vddd
15 Vssd
16* T6 (ERROR/57K/BE1)
17* T7 (CORREC/ARI-ID/BE0
18* SYNC
19* RDS-ID
20 DO
21 CL
22 DI
23 CE
24 SYR
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Vdda
3
REFERENCE
VOLTAGE
Vssa
4
ANTIALIASING
MPXIN 2
FILTER
DO
20
CL
21
DI
22
CE
23
T1 7
8
T2
T3~T7
9,10,11
16,17
Input/Output
Output Reference voltage output (Vdda/2)
Input Base band (multiplex) signal input
— Analog system power supply (+5V)
— Analog system ground
Output Sub-carrier input (comparator input)
Input Sub-carrier output (filter output)
Input Test input (to be always connected to ground)
Input Test input (standby control)
0: Normal operation/1: Standby state (crystal oscillation stop)
Input/Output Test I/O (RDS clock output)
Input/Output Test I/O (RDS data output)
Input/Output Test I/O (Soft judgment control data output)
Output Crystal oscillation output
Input Crystal oscillation input (external reference signal input)
— Digital system power supply
— Digital system ground
Input/Output Test I/O (Error existence/nonexistence output/playback carrier output/error block
number output)
Input/Output Test I/O (Error existence/nonexistence output/SK detection output/error block
number output)
Input/Output Block sync detection output
Output RDS detection output
Output Data output
Input Clock input
Input Data input
Input Chip enable
Input Sync and RAM address reset (positive logic)
FLOUT CIN
VREF
1 5
57kHz
BPF
SMOOTHING
(SCF)
FILTER
RAM
(24 BLOCK DATA)
CCB
MEMORY CONTROL
TEST
Figure 57 BLOCK DIAGRAM OF IC
Function
Serial data interface (CCB)
6
PLL
(57kHz)
VREF
ERROR CORRECTION
SYNC/EC CONTROLLER
(SOFT DECISION)
CLK(4.332MHz)
SYNC
DETECT-1
OSC/DIVIDER
13 12
XIN XOUT
– 57 –
CD-C471H
Vddd
CLOCK 14
RECOVERY
(1187.5Hz)
Vssd
15
DATA
RDS-ID
19
DECODER
SYNC
18
24 SYR
SYNC
DETECT-2