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All
and
more
about Sharp
PC-1500
at
http://www.PC-1500.info
RECEIVER
CLOCK
(RCLOCK):
Clock
input
with a
frequency
16
times
the
de·sired
receiver
shift
rate.
TPB
:
,\ positive
inJ)Ut
pulse
used
as
a
da ta
load
or
reset
strobe.
DATA
AVAI
LABLE(DA)
A
low·levcl
voltage at this ou tput
indica tes
tltat an entire
character has been
received
and
transferred
to
the Recei\•er Holding
Register.
SERIAL
DATA
IN
(SDI):
Serial
data r-cceived
on
this
input
line
enters
the
Receiver
Shift
Register
at
a
point
detennined
by
the
charac
ter
length.
A
high·
level
input
voltage
must
be
present when
data is
not
being
received
.
CLEAR
(CLEAiR):
A
low.level
voltage
at
this
input
resets
tl1e
Interrupt
Flip.Flop,
Receiver
Holding
Register,
Control
Register,
ancl
Sta tus
Register,
and sets
SERIAL DATA OUT
(SDO) high.
TRANSMITTER
HOLDING
REGISTER
EMPTY (THRE):
A
low.level
voltage
at th
is
output
indicates that tl1e
Transmitter
Holding
Register has
transferred its
contents to
the
Transmitter Shift
Register and
may
be
reloaded
with a
new character.
CHIP
SELECT
:I
(CS!)
:
A
high·level
voltage
at tllis
input
toge
ther wit.h
CS2
and
CS3 selects
the
UART.
REQUEST
TO SEND
(RTS):
Tltis
output
signal
tells
the
peripheral
to
to
get
ready to
receive
data.
CLEAR
TO
SEND
(CTS) is
the
response
from
the peripheral. RTS
is
set
to
a
low·level
voltage
when
data is
latched
in
the
Trans·
milter
Molding
Register or
TR is
set high,
and
is
reset
high when
both
tbe
Transrnitter
Holding
Register and
Transmitter Shift Register
are empty
and
TR
is
low.
SE
RI
AL
DATA
OUTPUT
(SDO)
:
The contents
of
the Transmitter
Shift
Reg;s1er
(start
bit,
data
bits,
parity
bit,
and stop bit(s) are
serially
shifted
out on
this
output. When no
character
is
being
transmitted,
at
high
level is
main·
taincd.
Start
of
transmission
is
defined
as
tlle
transit
ion
of
the
start
bit
from
a high.level to
a
low·
level
oulpul
vollage.
TRANSMITTE
R
BUS
(T BUS
0
·
T BUS 7):
Transmitter
parallel
data
inpu
t. These
may
be
externally
connected to
corresponding
Receive
r
bus
1cnninals.
RD/WR
:
A low.Jcvel
voltage
at
this
input
gates
data from
the
transmitter bus to the
Transmitter Molding
Register
or the
Con
trol
Register as
chosen
by
register
select.
A
high-level
vohage
gates
data
from
the
Receiver Holding Register
or
the
Sta
tus Register, as
chosen by
register
select,
10
the
receiver bus.
CH IP
SELECT
3 (CS3)
With
high·levcl
voltage
at
this
input
together
with
CS
I
and CS2
selects
the
UART.
PE
RIPHERA
L
STATUS
INTERRUPT
(PSI)
:
A high·tO·low transition
on
this
input
line
·
s ets
a
bit
in
the
Status
Register and
causes
an
INTER·
ROPT (INT
=
low}.
EXTERNAL STATUS
(ES):
A
low.Jcvcl
voltage at
tllis
input sets
a
bit
in
the
Status
Register.
CLEAR
TO
SEND (CTS):
When
this
input
from
peripheral
is
high,
transfer
of
a
character
to
the
Transmitter
Shiirt
Register
and
shifting
of
serial dala
on\
is
inhibited.
TRANSM ITTE!R
CLOCK (TCLOCK):
Clock
input
with
a
frequency
16 times
the
desired transmitter
shift
rate.
17
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