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UPD61181F1-105MN2A (MAIN ASSY : IC1001)
(EMMA2RL)
A
• 1 Chip System Codec
Block Diagram
Video
Decoder
CVBS or Y/C
B
DV
1394 Link
MPEG-TS
DV decode
BT.656
Stream
C
TE
L 13942296513
[Each Block]
1. MAIN CPU
CPU of 187MHz, 32bit, MIPS32
Attached with EJTAG debugger interface
2. Sub CPU
CPU of MIPS32
D
Operating for DSP section
3. Memory Controller
Correspond to DDR ×2 of 128Mbit – 512Mbit
Frequency is up to PC333(166MHz ×2)
4. ROM Interface (EMI)
FLASH ROM interface
5. GIO (EMI)
PCMCIA, etc
6. Peripheral
Universal input/output interface
Communication with TUFL-con
E
Watch-dog timer
7. Video Decoder
VDEC of 240MHz/10bit
Input is only YC 2ch, or V.
3D Y/C separation, 3D noise filter
Video signal
www
input
F
82
1
http://www.xiaoyu163.com
2
CPU
MIPS32
MPEG
AV
Encode
AV
1st
Switch
ATA
HDD
Y/C separation
Video siganl
processing
Input block
block
x
ao
y
Clock generator
.
i
DVR-230-S
2
http://www.xiaoyu163.com
3
8
Ext. Memory
DDR33
Unified
Memory
CPU
Controller
MIPS32
Stream
Processor
MPEG
Video
Decode
CSS/CPRM etc.
2nd
ATA
Peripheral
DVD
Q Q
3
6 7
1 3
8. MPEG AV Encoder
Video : MPEG1, 2
Audio : MPEG1, 2 Conversion to LPCM
9. Stream processor
Interface of stream
Decription of CSS, CPRM
En/Decription of CPRM, DES
10. MPEG Decoder
Video : MPEG1, 2, JPEG
This decoder is able to decode 2 signals simultaneously.
Audio : MPEG1, 2, LPCM, MP3, WMA, Dolby-digital
Test tone, Virtual surround
5.1ch Dolby-digital(option)
11. Video Encoder
Video DAC of 554MHz/10 bit
Correspond to 5ch Y, Pb, Pr(RGB, Component), YC(CVBS) of
NTSC/PAL/SECAM
VBI
detection
Clock
Conversion
Color
processing
demodulation
block
u163
I2C register
.
3
4
2 9
9 4
2 8
480P
Video
Encoder
480I
Display
Controller
BT.656 or
&
BT.1358
Scaler
PCM
Audio
Processor
S/PDIF
1 5
0 5
8
2 9
9 4
Video signal
Video signal
m
output
output block
co
4
9 9
2 8
9 9
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