Memory - LG GW520 Service Manual

3. BB Circuit Technical brief

3.7 Memory

2Gbit NAND Flash & 1Gbit DDR SDRAM employed on GW520 with 16 bit parallel data bus thru
ADD(0) ~ ADD(24). The 1Gbit Nand Flash memory with DDR SDRAM stacked device family offers
multiple high-performance solutions.
SD_ADD(0:13)
TP100
SD_ADD(0)
SD_ADD(1)
SD_ADD(2)
SD_ADD(3)
SD_ADD(4)
SD_ADD(5)
SD_ADD(6)
SD_ADD(7)
SD_ADD(8)
SD_ADD(9)
SD_ADD(10)
SD_ADD(11)
SD_DATA(0:15)
SD_ADD(12)
SD_ADD(13)
TP102
SD_DATA(0)
SD_DATA(1)
SD_DATA(2)
SD_DATA(3)
SD_DATA(4)
SD_DATA(5)
SD_DATA(6)
SD_DATA(7)
SD_DATA(8)
SD_DATA(9)
SD_DATA(10)
SD_DATA(11)
SD_DATA(12)
SD_DATA(13)
SD_DATA(14)
SD_DATA(15)
_BC0
_BC1
TP107
LDQS
TP108
UDQS
SDCLKI
SDCLKO
TP109
CKE
TP110
BA0
TP111
BA1
TP112
_RAS
TP113
_CAS
_WR
TP114
_RAM_CS
LGE Internal Use Only
2Gb NAND +1Gb DDR SDRAM
D4
A0
E4
A1
F4
A2
G4
A3
G8
A4
F8
A5
E8
A6
D8
A7
D9
A8
G7
A9
G5
A10
F7
A11
E7
A12
E9
A13
L4
DQ0
M4
DQ1
N4
DQ2
L5
DQ3
M5
DQ4
N5
DQ5
M6 H8BCS0SI0MAP_56M
DQ6
N6
DQ7
EUSY0347503
M7
DQ8
N7
DQ9
L8
DQ10
M8
DQ11
N8
DQ12
L9
DQ13
M9
DQ14
N9
DQ15
K6
LDQM
K7
UDQM
L6
LDQS
L7
UDQS
C6
_CLK
C7
CLK
D7
CKE
E5
BA0
F5
BA1
F6
_RAS
E6
_CAS
D6
_WED
D5
_CS
[Figure 3.7-1] Memory circuit diagram
GW520 service manual
U100
- 42 - Copyright © 2009 LG Electronics. Inc. All right reserved.
NAND_IO(0:15)
TP101 NAND_IO(0)
P10
I_O0
N10
NAND_IO(1)
I_O1
NAND_IO(2)
M10
I_O2
L10 NAND_IO(3)
I_O3
F10 NAND_IO(4)
I_O4
NAND_IO(5)
E10
I_O5
D10 NAND_IO(6)
I_O6
C10 NAND_IO(7)
I_O7
NAND_IO(8)
N11
I_O8
M11
NAND_IO(9)
I_O9
NAND_IO(10)
L11
I_O10
K11 NAND_IO(11)
I_O11
G11 NAND_IO(12) 1V8_SD
I_O12
NAND_IO(13)
F11
I_O13
E11 NAND_IO(14)
I_O14
D11 NAND_IO(15)
I_O15
G3
TP104
_CE _NAND_CS
M3 TP105
_WEN _WR
F3 TP106
_RE _RD
L3
ALE SD_ADD(0)
K3
CLE SD_ADD(1)
E3
R__B
N3
_WP
H2
VCCN1
1V8_SD
C5
VSS1
C9
VSS2
G2
VSS3
H10
VSS4
P7
VSS5
1V8_SD
P9
VSS6
P5
VSSQ
C4
VDD1
C8
VDD2
P6
VDD3
P4
VDDQ1
P8
VDDQ2
Only for training and service purposes
FCDP
_WP