LG 47LW6500-UA Service Manual page 46

Close to DDR Pin
+1.5V_FRC_DDR
+1.5V_FRC_DDR
R5301
1K
1%
MVREFCA
R5302
1K
1% C5301
0 . 1 u F
+1.5V_FRC_DDR
R5303
1K
1%
MVREFDQ
R5304
1K
1%
C5302
0 . 1 u F
+1.5V_FRC_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+1.5V_FRC_DDR
DDR3 1.5V De-Cap Place near Memory
C5303 C5304
0 . 1 u F 22uF
16V 10V
P l a c e C l o s e t o D D R P i n
IC5301
H5TQ1G63DFR-PBC
M8 N3 DDR3_A[0]
MVREFCA VREFCA A0
P7 DDR3_A[1]
A1
P3 DDR3_A[2]
A2
H1 N2 DDR3_A[3]
MVREFDQ VREFDQ A3
P8 DDR3_A[4]
A4
P2 DDR3_A[5]
R5305 A5
L8 R8 DDR3_A[6]
ZQ A6
R2 DDR3_A[7]
240
A7
1% T8 DDR3_A[8]
A8
B2 R3 DDR3_A[9]
VDD_1 A9
D9 L7 DDR3_A[10]
VDD_2 A10/AP
G7 R7 DDR3_A[11]
VDD_3 A11
K2 N7 DDR3_A[12]
VDD_4 A12/BC
K8 T3 DDR3_A[13]
VDD_5 A13
N1
VDD_6
N9 M7
VDD_7 A15
R1
VDD_8
R9 M2
VDD_9 BA0
N8
BA1
M3
BA2
A1
VDDQ_1
A8 J 7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT
H2 J 3
VDDQ_8 RAS
H9 K3
VDDQ_9 CAS
L3
WE
J 1
NC_1
J 9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
NC_6 DQSL
G3
DQSL
A9 C7
VSS_1 DQSU
B3 B7
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML
J 2 D3
VSS_5 DMU
J 8
VSS_6
M1 E3 DDR3_DQL[0]
VSS_7 DQL0
M9 F7 DDR3_DQL[1]
VSS_8 DQL1
P1 F2 DDR3_DQL[2]
VSS_9 DQL2
P9 F8 DDR3_DQL[3]
VSS_10 DQL3
T1 H3 DDR3_DQL[4]
VSS_11 DQL4
T9 H8 DDR3_DQL[5]
VSS_12 DQL5
G2 DDR3_DQL[6]
DQL6
H7 DDR3_DQL[7]
DQL7
B1
VSSQ_1
B9 D7 DDR3_DQU[0]
VSSQ_2 DQU0
D1 C3 DDR3_DQU[1]
VSSQ_3 DQU1
D8 C8 DDR3_DQU[2]
VSSQ_4 DQU2
E2 C2 DDR3_DQU[3]
VSSQ_5 DQU3
E8 A7 DDR3_DQU[4]
VSSQ_6 DQU4
F9 A2 DDR3_DQU[5]
VSSQ_7 DQU5
G1 B8 DDR3_DQU[6]
VSSQ_8 DQU6
G9 A3 DDR3_DQU[7]
VSSQ_9 DQU7
DDR3_A[0-13]
P l a c e C l o s e t o D D R P i n
R5309
56
DDR3_BA0
R5310
56
DDR3_BA1
C5315
DDR3_BA2
0 . 0 1 u F
DDR3_MCK
25V
DDR3_MCKB
DDR3_CKE
DDR3_ODT
DDR3_RASB
+1.5V_FRC_DDR
DDR3_CASB
DDR3_WEB
R5308 0
DDR3_RESETB
DDR3_DQSL
DDR3_DQSLB
DDR3_DQSU
DDR3_DQSUB
DDR3_DML
DDR3_DQL[0-7]
DDR3_DMU
DDR3_DQU[0-7]
P l a c e t h e s e r a i l d a m p i n g r e s i s t
i n t h e m i d d l e o f D R A M p a t t e r n
R5311 22
FRC_DMU
R5312 22
FRC_DQSL
R5313 22
FRC_DQSLB
R5314 22
FRC_DQSU
R5315 22
FRC_DQSUB
R5316 22
FRC_DML
R5317 22
FRC_ODT
R5318 22
FRC_RASB
R5319 22
FRC_CKE
R5320 22
FRC_MCLK
DDR3_MCK
R5321 22
FRC_MCLKB
DDR3_MCKB
R5322 22
FRC_DDR3_RESETB
AR5301
FRC_A[10]
FRC_BA1
FRC_A[12]
FRC_A[4]
22
AR5302
FRC_A[6]
FRC_A[8]
FRC_A[1]
FRC_A[11]
22
AR5303
FRC_A[0]
FRC_A[2]
FRC_A[13]
FRC_A[9]
22
AR5304
FRC_A[7]
FRC_A[5]
FRC_A[3]
22
AR5305
FRC_BA2
FRC_BA0
FRC_WEB
FRC_CASB
22
MStar URSA5
DDR3 4Mbit
DDR3_DMU AR5306
FRC_DQL[4] DDR3_DQL[4]
FRC_DQL[6] DDR3_DQL[6]
DDR3_DQSL
FRC_DQL[2] DDR3_DQL[2]
FRC_DQL[0] DDR3_DQL[0]
DDR3_DQSLB 22
DDR3_DQSU AR5307
FRC_DQU[5] DDR3_DQU[5]
FRC_DQU[3] DDR3_DQU[3]
DDR3_DQSUB
FRC_DQU[7] DDR3_DQU[7]
FRC_DQU[1] DDR3_DQU[1]
DDR3_DML 22
DDR3_ODT AR5308
FRC_DQU[4] DDR3_DQU[4]
FRC_DQU[6] DDR3_DQU[6]
DDR3_RASB
FRC_DQU[2] DDR3_DQU[2]
FRC_DQU[0] DDR3_DQU[0]
DDR3_CKE 22
DDR3_MCK AR5309
FRC_DQL[3] DDR3_DQL[3]
FRC_DQL[1] DDR3_DQL[1]
DDR3_MCKB
FRC_DQL[5] DDR3_DQL[5]
FRC_DQL[7] DDR3_DQL[7]
22
DDR3_RESETB
DDR3_A[10]
DDR3_BA1
DDR3_A[12]
DDR3_A[4]
DDR3_A[6]
DDR3_A[8]
DDR3_A[1]
DDR3_A[11]
DDR3_A[0]
DDR3_A[2]
DDR3_A[13]
DDR3_A[9]
DDR3_A[7]
DDR3_A[5]
DDR3_A[3]
DDR3_BA2
DDR3_BA0
DDR3_WEB
DDR3_CASB
2 0 1 0 . 0 8 . 1 8
53 55