Block Diagram - Panasonic SA-AK640PL Service Manual

Cd stereo system
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16 Block Diagram

OPTICAL PICKUP
SEMICONDUCTOR
LASER
POWER DRIVE
B
PHOTO DETECTOR
A
B
B
B
F
B
E
B
IC7002
BA5948FPE2
4 CH DRIVE
F-
16
D3-
[CH3]
FOCUS COIL
F+
15
D3+
18
D4-
T-
[CH4]
TRACKING
COIL
T+
17
D4+
TRV+
14
D2+
M
M7302
[CH2]
SPINDLE
TRV-
13
D2-
MOTOR
SP+
12
D1+
M
M7301
TRAVERSE
[CH1]
MOTOR
SP-
11
D1-
LPD
Q7601
LASER
LD
B
A
C
B
D
F
E
VREF 26
B
IN3
28
FOP
LEVEL
SHIFT
IN4
27
TRP
LEVEL
SHIFT
IN2 1
TRVP
LEVEL
SHIFT
IN1 3
SPOUT
LEVEL
SHIFT
MUTE
PC1 4
PC
[CH1]
PC2 2
MUTE
[CH2]
X7201
81
80
79
NTEST2
B
82
B
NTEST
61
NSRVMONON
/RST
72
TIMING
NRST
GENERATOR
B
[GEN]
47
B
AVDD2
31
AVSS2
A, B, C, D, E, F
35~40
A,B,C,D,E,F
LD
42
LD
LPD
41
PD
ARFF
50
ARFFB
ARFF
49
ARFOUT
CMOS
RF
48
ARFDC
AMPLIFIER
RFOUT
45
46
RFIN
43
CENV
33
CTRCRS
B
32
OSCIN
B
34
VREF
B
44
RFENV
A/D
CONVERTER
PC
22
PC
SPOUT
21
SPOUT
TRVP
23
TRVP
TRP
24
TRP
OUTPUT
PORT
FOP
25
FOP
SRVMON0
29
SRVMON1
30
DIGITAL
OUT
66
IC7001
MN6627954MA
SERVO PROCESSOR/
DIGITAL SIGNAL
PROCESSOR/
DIGITAL FILTER
D/A CONVERTER
53
B
B
70
69 67 68
51 53 52 54
55
MICRO COMPUTER
TXTCK
DSL/PLL/VCO
INTERFACE
[DSLPLL]
[MCIF]
TXTD
DQSY
SPINDLE
EFM DEMODUALTION
CPU
SYNC INTERPOLATION
[DSV]
CIRC ECC
(SBCK)
SUBCODE
CDROM ECC
INTERFACE
[DEMECC]
[DEMECC]
(SUBC)
CIRC RAM
(TXNCLDCK)
SERVO
FLAG
CPU
65
[DSV]
BLKCK
71
BUS CONTROL UNIT
PRAMVDD33
20
[BCU]
1Mbit
PRAMVSS33
18
DRAM
D0~D15
83~92,94~99
A0~A11
1~7,11~15
BA0,BA1
16,17
MP3/WMA
NWE,NCAS
8,9
DECORDER
10,100
NRAS,SDRCK
FS
SERIAL OUTPUT
EXT0
62
CONVERTER
INTERFACE
EXT1
[FSC]
[DAO]
63
EXT2
64
(LRCK)
DIGITAL FILTER
1bitDAC
(BCLK)
PWM LOGIC
[DF, MASH]
(SRDATA)
76
REGULATOR
(DVDD2)
ANALOG
LOWPASS
FILTER
57
58
59 56
60
78
26
76
28
93
27
77
CD SIGNAL
B
B
B
B
B
RCH
SA-AK640PL
TOMAINBLOCK
A
B
B

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