Icom IC-2200H Service Manual page 15

4-6 UT-115 CIRCUIT DESCRIPTION
4-6-1 RECEIVER CIRCUIT
The detected digital signals "FMDET" from the connected
transceiver via the J301 (pin 22) are amplified at the buffer
amplifier (IC251, pin 2). The amplified signals are applied to
the GMSK modem circuit (IC252, pin 11), and are then
applied to the CPU (IC204) as clock synchronizer digital sig-
nal. The digital signals from the CPU are applied to the
AMBE voice CODEC IC (IC151) to precess code extention,
and are then applied to the linear CODEC IC (IC50) as 32
bits digital voice data. The applied digital signals are con-
verted to the analog AF signals at the D/A converter section
(IC50), and are then applied to the connected transceiver
via the J301 (pin 21) as "DAFOUT" signal.
4-6-2 TRANSMITTER CIRCUIT
The analog AF signals "AMODIN" from the connected trans-
ceiver via the J301 (pin 4) are amplified at the buffer ampli-
fier (IC251, pin 6). The amplified signals are applied to the
linear CODEC IC (IC50, pin 5) to convert 32 bits digital voice
data at the A/D converter section via the "ADIN" line. The
digital signals are applied to the AMBE voice CODEC IC
(IC151) to process code compression, and are then applied
to the CPU (IC204). The digital signals from the CPU con-
vert to the GMSK base band signal at the GMSK modem
(IC252), and are then amplified at the buffer amplifier
(IC253, pin 5). The amplified signals are applied to the con-
nected transceiver via the J301 (pin 3).
4-6-3 RESET CIRCUIT
The UT-115 has the reset IC (IC203). The IC outputs reset
signal to the CPU (IC204, pin 7) when "VDD" port (pin 2)
becomes more than 2.8 V.
4-6-4 RS-232C CIRCUIT
IC351 is a RS-232C compatible serial interface IC which
converts data between the CPU and the external equipment
(EX: Personal Computer).
4-6-5 LEVEL CONVERTER CIRCUIT
The level converter circuit (Q305 and Q306) converts com-
munication data level between the CPU (IC204) and the
connected transceiver's CPU.
Q301, Q302 and Q303 convert control signals level between
the UT-115 and the connected transceiver.
• UT-115 BLOCK DIAGRAM
-"TXD_2" signal to
the J301, pin 16
-"RXD_2" signal to
the J301, pin 17
-"232C_RX" signal
to the J301, pin 25
-"232C_TX" signal
to the J301, pin 26
"DAFOUT" signal to
the J301, pin 22
CPU
Level
CODEC
converter
Q305, Q306
DSP
CODEC
RS-232C
IC351
Linear
CODEC
4-7 UT-115 POWER SUPPLY CIRCUITS
VOLTAGE LINES
Line
The 5 V voltage from the connected transceiver
via the J301 (pin 29). The 5V line is controlled by
the +5V control circuit (Q50 and Q51). The cir-
5V
cuit is controlled by the "PSAVE" signal from the
CPU (IC204, pin 58 and 59).
Common 3.3 V converted from the 5V line by the
3.3V regulator circuit (IC1). One of the 3.3 V line
is controlled by the +3V control circuit (Q400 and
3.3V
Q401). The circuit is controlled by the "PSAVE"
signal from the CPU (IC204, pin 58 and 59).
Common 3.2 V converted from the 4.5–8 V line
by the 3.2V regulator circuit (IC2). The circuit is
3.2V
controlled by the "APWR" signal from the CPU
(IC204, pin 16).
4-8 UT-115 PORT ALLOCATIONS
4-8-1 MODEM IC (IC252)
Pin Port
number name
Outputs 2.4576 MHz clock signal to
2 MCLK
the CPU (IC151, pin 39).
7
ACQ
19 TXDT
20 RXDT
21 RXCK
22 TXCK
Modem
IC204 IC252
IC151
IC50
4 - 7
Description
Description
Outputs the PLL band width control
signal while receiving.
Outputs transmitting data signal to the
CPU (IC204, pin 54).
Input port for receiving data signal
from the CPU (IC204, pin 53).
Input port for receive clock signal from
the CPU (IC204, pin 52).
Outputs transmit clock signal to the
CPU (IC204, pin 51).
"DMOD" signal
Buffer
to the J301, pin 3
IC253B
"FMDET" signal
Buffer
from the J301, pin 23
IC251A
"AMODIN" signal
Buffer
from the J301, pin 4
IC251B