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Intel 740 Design Manual

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Intel740™ Graphics Accelerator
Design Guide
August 1998
Order Number:
290619-003

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Summary of Contents for Intel 740

  • Page 1 Intel740™ Graphics Accelerator Design Guide August 1998 Order Number: 290619-003...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    Contents Introduction ........................1-1 About This Design Guide ................1-1 References....................1-2 Addin Card Design.....................2-1 Introduction ....................2-1 2.1.1 Design Features................2-2 2.1.1.1 Intel740™ Graphics Accelerator........2-2 2.1.2 BT829B - Video Decoder ..............2-3 2.1.2.1 BT869 - TV Encoder ............2-3 2.1.3 Terminology ..................2-3 2.1.3.1 Power Sources ...............2-3 2.1.3.2 Fences ................2-4 2.1.3.3...
  • Page 4 3 Device AGP MotherBoard Design ................3-1 Introduction ....................3-1 3.1.1 Overview ..................3-1 3.1.2 About This Chapter ................3-2 3.1.3 Block Diagram .................3-2 3.1.4 Implementation Issues ..............3-3 3.1.4.1 Disabling A Master Device ..........3-3 3.1.4.2 Low Power Logic Implementation........3-4 3.1.4.3 GPO27# and GPO28# Signal Duration ......3-5 3.1.5 State Diagrams ................3-5 3.1.5.1...
  • Page 5 Major Signal Sections .................3-10 ® Example ATX Placement for a UP Pentium II Processor / ® Intel 440BX AGPset / Intel 740 Graphics Accelerator Design ....3-11 Four Layer Board Stack-up.................3-12 3-10 Point-to-Point Topology ................3-15 3-11 3 Device Data Load Topology..............3-16 3-12 3 Device Strobe Load Topology..............3-16...
  • Page 6 3-21 2/4 MB Local Memory Connection (64-bit data path) .........3-21 3-22 512Kx32 and 256Kx32 Pinout Compatibility..........3-26 3-23 1M X 16 Pinout Compatibility..............3-26 Mounting Hole Locations (Fan/Heatsink Assembly) ........5-1 VMI Header Placement.................5-2 DVD Daughter Card Dimensions (ATX and NLX)—Top Side ......5-2 50 Pin Video Connector Schematic ..............5-3 Recommended Bracket Placement ..............5-4 Recommended Bracket Cutout..............5-4...
  • Page 7 Tables Mix and Match Options For Intel740™ Graphics Accelerator Card ....2-2 Intel740™ Graphics Accelerator Power Supplies .........2-3 Bt829B GND and AGND Pins..............2-12 Bt829B VCC and AVCC Pins..............2-12 Bt869 Digital and Analog Power Pins ............2-13 AGP Signal Lengths..................2-13 Strobes and Corresponding Signal Groups ..........2-13 Supported Memory Options (Other Memory Options Are Not Supported)....................2-14 Memory Layout Restrictions (See...

  • Page 8: Revision History

    Revision History Date Revision Description 2/98 -001 Initial Release. Part 2: Added Figure 2-2; added “Note” verbiage in 2.14. Part 3: Added verbiage to 3.3.5; Modified Figures 4/98 -002 3-14, 3-15, 3-16, 3-19; Modified Table 3-10. Part 5: Modified Figure 5-6. Restructured document and added a motherboard design: Chapter 2 contains the Addin Card design.

  • Page 9: Introduction

    Introduction...

  • Page 11: About This Design Guide

    Heatsink, VMI Header Placement, Video Connector, brackets, and NLX considerations. • Chapter 6, "Third Party Vendor Information"— This section includes information regarding various third-party vendors who provide products to support the Intel 440BX AGPset and the Intel740 graphics accelerator. •...

  • Page 12: References

    Intel740™ Graphics Accelerator Application Note 653 - Thermal Design Considerations: See Appendix A • Intel 440BX AGPset Design Guide. Contact your field sales representative (Literature order #290634). or visit the 440BX AGPSet WEB page at: http://developer.intel.com/design/pcisets/designex/290634.htm Intel740™ Graphics Accelerator Design Guide...
  • Page 13 Intel740™ Graphics Accelerator Addin Card Design...

  • Page 15: Addin Card Design

    Addin Card Design Addin Card Design This chapter provides a complete package of design information for the Intel740™ graphics accelerator. Usage of the Intel740™ graphics accelerator on an ATX and NLX graphics card is discussed. The basis of this document is a reference ATX card. Introduction The reference design card described in this document contains the following features.

  • Page 16: Design Features

    • TV Out Interface. Intel has worked with Rockwell* (Brooktree*) to design an interface capable of supporting a high quality TV out chip. This interface allows the Intel740™ graphics accelerator to output on a monitor, TV, or both.

  • Page 17: Bt829B - Video Decoder

    Addin Card Design 2.1.2 BT829B - Video Decoder The Bt829B is a video capture processor used to convert analog video data into CCIR 601 digital video data. This chip contains the following capabilities. • Analog Inputs. The Bt829B contains four composite video inputs along with one chroma and one luma input for s-video.

  • Page 18: Fences

    Addin Card Design 2.1.3.2 Fences A “fence” is a line routed out of the plane such that a given area is isolated from the rest of the plane except at a single point of contact, conceptually the “gate” in the fence. A fence will minimize noise originating from digital signaling onto the analog signals.

  • Page 19: Layout And Routing Guidelines

    Addin Card Design Layout and Routing Guidelines This chapter describes layout and routing recommendations to insure a robust design. These guidelines should be followed as closely as possible. Any deviations from the guidelines listed here should be simulated to insure adequate margin is still maintained in the design. 2.2.1 Placement The ball connections on the Intel740™...

  • Page 20: Board Description

    Addin Card Design An example of the proposed component placement for an ATX form factor design is shown in Figure 2-4. This is the placement used on the reference card. For NLX placement issues, refer to Section 5.6, “NLX Considerations” on page 5-5.

  • Page 21: Four Layer Board Stack-Up

    Addin Card Design Figure 2-5. Four Layer Board Stack-up Primary Signal Layer (1/2 oz. cu.) Z = 65 ohms 6 mils PREPREG Ground Plane (1 oz. cu.) 50 mils CORE Power Plane (1 oz. cu) 6 mils PREPREG Secondary Signal Layer (1/2 oz. cu) Z = 65 ohms Total board width = 62 .6 mils...

  • Page 22: Bga Component

    Addin Card Design 2.2.3 BGA Component 2.2.3.1 Layout Requirements The following layout requirements should be followed when routing the 468 MBGA package. • All non-ground BGA lands should be Metal Defined (MD) lands with the following nominal dimensions (see Figure 2-6).

  • Page 23: Ground Connections

    Addin Card Design 2.2.3.2 Ground Connections All lands in the four corners and center are V (GND). Thermal analysis requires that each V ball connect to an adjacent via which passes through to the solder side of the board, one via per ball, with a trace as wide as the via.

  • Page 24: Decoupling

    Addin Card Design Figure 2-9. Suggested VCC Planes for the Intel740™ Graphics Accelerator V C C 2 V C C 3 VCC2 on VCC Layer VCC3 on Secondary Side Signal Layer vcc_pl.vsd 2.2.3.4 Decoupling Decoupling capacitors should ideally be placed as close as possible to the Intel740 graphics accelerator.

  • Page 25: General Signal Routing

    Addin Card Design 2.2.3.5 General Signal Routing Figure 2-11 depicts general escape of traces from the five rows of BGA ball pads. The first three ball rows can be routed on the primary layer. The last two must be routed through vias to the secondary layer.

  • Page 26: Ground Planes

    Addin Card Design 2.2.5.1 Ground Planes The Bt829B and associated circuitry have two ground planes, GND and ANALOG_GND (AGND). These are electrically the same plane but should be separated by a fence, as described in Section 2.1.3.2, “Fences” on page 2-4.

  • Page 27: Power Planes

    Addin Card Design 2.2.6.2 Power Planes The Bt869 and associated circuitry have two power planes, VCC3 and 3VAA_BT869. The 3VAA_BT869 plane is a separate cutout, joined to VCC3 by a ferrite bead. The device should reside entirely above the 3VAA_BT869 plane, as there are no VCC3 connections to the device. So long as the 3VAA_BT869 plane underlies all the analog components, it should be as small as possible.

  • Page 28: Intel740™ Graphics Accelerator Memory Layout And Routing Guidelines

    Addin Card Design For example, AD29 and AD_STB_B must not be mismatched by more than 0.5”. No such comparison, however, should be enforced between AD29 and AD30, or AD29 and C/BE2#, etc. Note: AGP strobes must be separated by 2X normal signal spacing (i.e., if normal spacing is 5/10 or 6/12, the strobe signals must be separated from other traces by 20 or 24 mils, respectively).

  • Page 29: Layout Dimensions (Ma[11:0])

    Addin Card Design Figure 2-12. Layout Dimensions (MA[11:0]) SGRAM 4.0” 0.25” - 0.9” Intel740™ 0.25” - 0.6” Intel740 Chip 0.25” - 0.6” SO-DIMM SGRAM Figure 2-13. Layout Dimensions (MD[63:0], DQM[7:0]) 3.0” 0.9” 0.4” Intel740™ Intel740 Chip SGRAM 0.4” SGRAM SO-DIMM Table 2-10.

  • Page 30: Layout Dimensions (Web#, Srasb#, Scasb#, Csa0#)

    Addin Card Design Figure 2-15. Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#) SGRAM 2.0” - 4.0” Intel740 0.25” - 0.6” ™ Intel740 0.25” - 0.9” Chip 0.25” - 0.6” SGRAM Table 2-11. Memory Layout Restrictions (See Figure 2-16 and Figure 2-17) Intel740™...

  • Page 31: Intel740™ Graphics Accelerator Memory Configurations

    Addin Card Design Signal Intel740™ to Resistor OCLK to Resistor 2.75” ±0.25 RCLK0, RCLK1 3.0” ±0.25” Note: It is important to match clock lengths. For example, if the length from OCLK to Resistor is 1.03, then the length from Resistor to RCLK should be 3.03. Figure 2-18.
  • Page 32 Addin Card Design Configuration #2: Two rows of memory are supported in this configuration. If 256Kx32 components are used 4MB of memory is obtainable, if 512Kx32 is used, then 8MB is supported. Note that both rows of memory receive different copies of each control signal, for loading reasons. Figure 2-20.
  • Page 33 Addin Card Design Configuration #3: One row of memory is supported in this configuration using 1Mx16 SDRAMs. Only the maximum allowable amount of memory (8MB) is supported in this configuration. Note that each copied signal is sent to only two components. Figure 2-21.

  • Page 34: Tv Out Interface

    Addin Card Design 2.2.6.7 TV Out Interface The TV out bus is the group of signals that carry digitized display data from the Intel740 graphics accelerator to the Bt869 flicker filter TV-out component. This interface is shared with the BIOS interface. Table 2-12 gives the maximum trace lengths between components.

  • Page 35: Addin Card Schematics

    Addin Card Design Addin Card Schematics This section describes the Intel740™ Graphics Accelerator Reference Design Schematics. Please read this section carefully to observe all design recommendations and requirements. The description of each schematic page is named by the logic block shown on that page. Cover Sheet (Schematic Page 1) The Cover Sheet shows the schematic page titles, page numbers, disclaimers and power pins.
  • Page 36 Addin Card Design Voltage Regulator (Schematic Page 5) This page shows the circuitry to convert from 3.3 Volts to 2.7 Volts. The regulator used in the reference design does not need any heat sink for the FET. As shown, the FET will be dissipating slightly over 1 watt.
  • Page 37 Addin Card Design AGP Card Edge (Schematic Page 9) This page details the connections of AGP. All power is derived from this connector. Using the rule of 1A per pin, the 12 volt supply is capable of supplying 1A, the 5 Volt supply is capable of supplying 2A and the 3.3 Volt supply is capable of supplying 8A.

  • Page 38: 512Kx32 And 256Kx32 Pinout Compatibility

    Addin Card Design Figure 2-23. 512Kx32 and 256Kx32 Pinout Compatibility Pin 51 A 8 / A P A 9 / A P Intel740™ A 9 / B S Pin 29 A 1 0 / B S Intel740 Chip A 1 0 Pin 30 5 1 2 K x 3 2 S G R A M...
  • Page 39 Addin Card Design Video Connector (Schematic Page 14) This page shows a specially designed solution to the problem of too many connectors and not enough board space. This 50 pin connector allows external hookup for a tuner, S-Video in, S-Video Out, composite video in, and composite video out.
  • Page 40 Addin Card Design Intel740™ Graphics Accelerator Design Guide 2-26...
  • Page 41 OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PRPERTY RIGHTS IS GRANED HEREIN. INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF INFORMATION IN THIS SPECIFICATION.
  • Page 42 VMI CONNECTOR p. 8 VIDEO VOLTAGE REGULATOR DECODER VIDEO CONNECTORS p. 5 p. 6 p. 14 CNTL INTEL740(TM) ADDR GRAPHICS TV TUNER MEMORY Graphics Accelerator CONNECTOR DATA p. 13 p. 14 p. 3, 4 VGA/DDC CONNECTOR p. 10 FLASH BIOS p.
  • Page 43 SUBSYSTEM ID IS 0X100 VCC_CORE VCC3 VDDQ VCC3 VCC3 6,11 3VVP[15:0] AD[31:0] VENDOR ID IS 0X8086 3VVP0 NOTE: 3VVP1 3VVP2 ----- 3VVP3 THIS I.D. NEEDS TO 3VVP4 REFLECT BOARD VENDOR 3VVP5 3VVP6 VCC3 VDDQ 3VVP7 3VVP8 VCC3 3VVP9 3VVP10 AD10 VP10 AD10 3VVP11...
  • Page 44 VCC3 VCC3 66.6667MHZ VCC3 MA[11:0] 12,13 AA23 AD17 12,13 AF16 AC17 XTAL1 AE16 12,13 MD[63:0] AD18 AD06 AF17 AE06 AC18 AC07 AE17 AF06 AD19 AD07 AF18 AF07 AC19 MA10 MA10 AC08 AE18 MA11 MA11 AE07 AE19 WEA# 12 WEA# AD08 AF19 WEB# 13 WEB#...
  • Page 45 POWER CONFIGURATION* ____________________________________________________ CORE STUFF EMPTY STUFF EMPTY 3.3V 2.7V EMPTY STUFF STUFF EMPTY 2.7V 2.7V STUFF EMPTY EMPTY STUFF 3.3V 3.3V EMPTY STUFF EMPTY STUFF 2.7V 3.3V *DEFAULT +12V VCC3 VCC_CORE LT1575 SHDN IPOS 100UF INEG L_GATE GATE * THE DEFAULT POWER CONFIGURATION COMP1 COMP IS NOT REPRESENTED HERE...
  • Page 46 NOTE: ANALOG PLANE NEEDS TO BE FENCED FROM THE DIGITAL PLANE VCC3 BT829B MUX3 MUX2 MUXOUT_YIN SV_LUM MUX2 MUXOUT MUX1 CV_IN MUX1 MUX0 TUNER MUX0 AGCCAP AGCCAP SV_CHR REFOUT TP_0559 TP_0582 SYNCDET HRESET* 3VVREF 3,11 VRESET* 3VHREF 3,11 YREF+ ACTIVE 3VVCLK 3,11 YREF- QCLK...
  • Page 47 VCC3 3VAA_BT869 NOTE: MAKE 3VAA_BT869 A CUTOUT IN POWER PLANE NOTE: ANALOG PLANE NEEDS TO BE FENCED FROM THE DIGITAL PLANE PRIMARY SIGNALS SHOULD NOT CROSS CUTOUT 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .01UF 10UF .1UF .01UF 3VAA_BT869 BT868/869 P<23>...
  • Page 48 +12V VCC3 2X20RCPT VMIHA[3:0] VMIHA0 THERMISTOR VMIHA1 VMIHA2 VMIHA3 5VVP[7:0] 5VVP0 PHYSICAL PINOUT VIEW OF THE 40 PIN HEADER (COMPONENT SIDE) 5VVP1 VMI3V 3.3V 5VVP2 3.3V Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 5VVP3 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 5VVP4...
  • Page 49 +12V VCC3 VDDQ NOTE: ---- C120 C122 C129 USE TANTALUM CAPS +12V VCC3 VDDQ 22UF 22UF 22UF AGP CARD EDGE AD[31:0] GOLD AD31 AD31 AD30 AD30 VCC5 AD29 AD29 VCC5 AD28 AD28 AD27 AD27 AD26 AD26 AD25 AD25 AD24 AD24 AD23 AD23 AD22...
  • Page 50 VCC3 VCC3 BAV99 THERMISTOR BAV99 BAV99 SOT23S HIDDEN PINS: GND: 16,17 USED FOR BRD MOUNT BAV99 FUSE_5 BAV99 L_RED 22PF 22PF L_GREEN MON0PU L_BLUE 5VDDCDA 11 MON2PU GREEN VGA_HSYNC HSYNC 4 22PF 22PF VGA CONN VGA_VSYNC VSYNC 4 5VDDCCL 5VDDCCL 11 BLUE 22PF 22PF...
  • Page 51 QS3861 5VVP[15:0] 3VVP[15:0] 3,6 5VVP0 3VVP0 5VVP1 3VVP1 5VVP2 3VVP2 5VVP3 3VVP3 .1UF .01UF 5VVP4 3VVP4 5VVP5 3VVP5 5VVP6 3VVP6 5VVP7 3VVP7 5VVRDY 3VVRDY 3 1.62K 5VVREF 3VVREF 3,6 QS3861 QS3861 5VVP[15:0] 3VVP[15:0] 3,6 5VVP15 3VVP15 5VVP14 3VVP14 5VVP13 3VVP13 5VVP12 3VVP12 5VVP11...
  • Page 52 VCC3 SO-DIMM CONN. 4,13 MA[11:0] MD[63:0] 4,13 MA11 MD63 RSVD(A11) DQ63 MA10 MD62 RSVD(A10) DQ62 MD61 DQ61 MD60 DQ60 MD59 DQ59 MD58 DQ58 MD57 DQ57 MD56 DQ56 MD55 DQ55 MD54 DQ54 MD53 DQ53 MD52 DQ52 MD51 DQ51 MD50 SRASA# RAS* DQ50 MD49 SCASA#...
  • Page 53 VCC3 VCC3 C118 .1UF .01UF .1UF .01UF VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 SGRAM 512Kx32 SGRAM 512Kx32 MD[31:0] 4,12 MD[63:32] 4,12 VCC3 VCC3 VCC3 VCC3 MD31 MD63 TCLK1 DQ31 DQ31 MD30 MD62 DQ30 DQ30 MD29 MD61 VDDQ DQ29 VDDQ DQ29 MD28 MD60 VREF/MCH...
  • Page 54 +12V C103 THERMISTOR 22PF CONX_20 TVOUT_Y 7 1.8UH C102 C104 330PF 220PF 5VSCL 5VSDA TVTUNERIN TUNER SVINC 3.3UH 22PF 330PF 330PF CONX_24 TVOUT_C 7 1.8UH 330PF 220PF SV_LUM 3.3UH 330PF 330PF 22PF CONX_47 SV_CHR TVOUT_CVBS 7 3.3UH 1.8UH TVTUNER12V 330PF 330PF 330PF 220PF...
  • Page 55 +12V VCC3 C119 .1UF 22UF .01UF .1UF .01UF PLCC SOCKET FOR BIOS ROMOE# ROMWE# 4,6,7,8 GPIO8 ROMA[17:0] ROMA16 5VROMD7 ROMA15 5VROMD6 ROMA14 5VROMD5 ROMA13 5VROMD4 ROMA12 5VROMD3 ROMA11 5VROMD2 ROMA10 5VROMD1 ROMA9 5VROMD0 ROMA8 ROMA7 QS3861 ROMA6 ROMA5 5VROMD7 3VROMD7 ROMA4 5VROMD6 3VROMD6...
  • Page 56 1.1 REVISIONS 1.5 REVISIONS PULL-DOWN REISITOR ON GPIO4 REMOVED C39, C41, C42, & C44 CHANGED TO 15PF ON P.5, NO PACKAGE SIZE CHANGE NEEDED SIGNAL GPI08 ADDED TO VMI 2X20 HEADER ON PIN Z18 SIGNALS XT1CAP AND XT0CAP RELOCATED SINCE XTAL FILTERS CHANGED ON P.5 FAN FAIL SIGNAL REMOVED FROM QSWITCH OE# ON INTEL740(TM) GRAPHICS ACCELERATOR OSCILLATOR PULLED HI TO 3.3V L3 AND L4 ON P.5 CHANGED TO 4.7UH NAD LOCATION IN XTAL FILTER CIRCUIT CHANGED...
  • Page 57 Intel740™ Graphics Accelerator 3 Device AGP Motherboard Design...

  • Page 59: Device Agp Motherboard Design

    Since the focus of this section is only the 3-point AGP implementation with the Intel740 graphics accelerator, many of the layout and routing guidelines for the motherbaord are ® referenced to the Intel 440BX AGPset Design Guide. 3.1.1...

  • Page 60: About This Chapter

    Section 1, "Introduction"—This section provides an overview of the features of a 3-point AGP reference design (DS1P/440BX/I740). Chapter 1 also provides a general component overview of the Pentium II processor, Intel 440BX AGPset, and the Intel 740 graphics accelerator. This section also provides implementation issues associated with a 3-point AGP design and design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segment.

  • Page 61: Implementation Issues

    The graphics controller that is used as the down device on the motherboard must have a mechanism that disables the device in a manner acceptable to the implementation of a logical point-to-point bus. The Intel 740 has such a mechanism that Intel740™ Graphics Accelerator Design Guide...

  • Page 62: Low Power Logic Implementation

    3 Device AGP MotherBoard Design allows it to be put in a low power state. In this low power state, the Intel740 chip is disabled and will not initiate or respond to cycles on the AGP bus. In addition, the power consumption of this device in this state is less than 1 Watt.

  • Page 63: Gpo27# And Gpo28# Signal Duration

    3 Device AGP MotherBoard Design Figure 3-3. The Schematic Diagram for the WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST Vcc3 Vcc3 2.2 K Ω TEST OUT1 WEB# OUT2 SCASB# Intel740™ OUT3 SRASB# Chip SYSCLK OUT4 CLR# CS0B# OUT5 CS1B# OUT6 PIIX4E GPO28# 3.1.4.3...

  • Page 64: State Diagrams

    3 Device AGP MotherBoard Design 3.1.5 State Diagrams Figure 3-4. Intel740™ Graphics Controller (On Board Device) Remains in Low Power Mode System Reset Low Power Mode At system RESET, the Intel740™ graphics controller on the motherboard is always put into the low power state.

  • Page 65: Signal Quality And Timing Issues

    3 Device AGP MotherBoard Design 3.1.5.1 Signal Quality and Timing Issues There are two modes of operation for the AGP bus, each with it's own signal quality and timing issues. These two operating modes are 1X mode and 2X mode. Because 1X mode is a common clock mode, flight time of the signal is of the most importance.

  • Page 66: Clock Issues

    3 Device AGP MotherBoard Design 3.1.5.3 Clock Issues Supplying a clock to both AGP master devices raises issues that must be considered when implementing a logical point-to-point bus. Among these issues are clock signal quality, routing, and clock skew. Signal quality and routing are of a major concern since the clock now must be routed to both master components.

  • Page 67: Design Recommendations

    Since the concentration of this section is mainly 3 Device AGP implementation, refer to the Intel 440BX AGPset Design Guide for the remaining design guidelines. It would be beneficial to have that design guide before tying to read this section.

  • Page 68: Bga Quadrant Assignment

    82443BX Memory Subsystem Layout and Routing Guidelines — 100/66 MHz 82443BX Memory Array Considerations — 3 DIMM Memory Layout & Routing Considerations — PCI BUS Routing Guidelines — Decoupling Guidelines for an Intel 440BX AGPset Platform — Intel 440BX AGPset Clock Layout Recommendations • Design Checklist •...

  • Page 69: Example Atx Placement For A Up Pentium

    1. The ATX placement and layout below is recommended for single (UP) Pentium II Processor / Intel 440BX AGPset/ Intel740 Graphics Accelerator system design. 2. The example placement below shows 1 Slot 1 connector, 2 PCI slots, 1 Shared slot, 3 DIMM sockets, and one AGP connector.

  • Page 70: Board Description

    3 Device AGP MotherBoard Design 3.2.2 Board Description For a single Pentium II / Intel 440BX AGPset /Intel 740 Graphics Accelerator motherboard design, a 4 layer stack-up arrangement is recommended. The stack up of the board is shown in Figure 3-9.

  • Page 71: Data And Strobe Definitions

    3 Device AGP MotherBoard Design results. The benefit to the former method is that a solution space can be determined before any placement and routing is attempted. This saves time and effort over the method of route, simulate, adjust. It is, therefore, recommended that the simulation results for the 3-load bus drive the layout and routing.

  • Page 72: Assumptions For Board Design Guidelines

    3 Device AGP MotherBoard Design 3.2.3.3 Assumptions for Board Design Guidelines These guidelines are primarily for Accelerated Graphics Port (AGP) designs that use an Intel740 graphics controllers on a 82443BX motherboard and an AGP-compliant add-in card. They assume certain requirements in order to produce an AGP compliant placement and routing solution. These assumptions were used for the initial pre-route analysis of the design.

  • Page 73: Point-To-Point Topology

    3 Device AGP MotherBoard Design Longer lines have more crosstalk, therefore longer line lengths require a greater amount of spacing between traces to maintain skew timings We assumed a 4 layer boardstackup as described earlier. Control Signal and Clock Requirements Table 3-7.

  • Page 74: 3-Load Agp Topology

    3 Device AGP MotherBoard Design 3.2.3.6 3-Load AGP Topology Figure 3-11 Figure 3-12 show the topologies for a 3-load AGP bus. The motherboard is divided into 2 trace segments as shown. These are referred to as segment A and B. The motherboard contains one AGP connector and one AGP master device.

  • Page 75: Device Data Load Topology (Solution 1 Is Shown)

    3 Device AGP MotherBoard Design Assume: GAD1 segment A=4.1" segment B=2.7" (A+B=6.8") and GAD2 segment A=3.5" and segment B=3.0" (A+B=6.5"). Notice that GAD1 A and GAD2 have more than 0.5" difference, but A+B is only 0.3" difference. Also, the strobes should be the longest signal in the group. Figure 3-13.

  • Page 76: Intel740™ Graphics Accelerator Memory Layout And Routing Guidelines

    3 Device AGP MotherBoard Design Table 3-9. Clock Segment Solution Space Clock Net Driver to resistor lengths Resistor to Load lengths Gclkin 0.4-0.5 Inches 6.2-6.4 Inches Gclks 0.3-0.4 Inches 4.4-4.6 Inches Gclk740 0.4-0.5 Inches 6.4-6.6 Inches The clock lines were tuned as detailed in table Table 3-9 to ensure that no clock skew exceeding 0.75 ns occurred.

  • Page 77: Layout Dimensions (Ma[11:0])

    3 Device AGP MotherBoard Design Table 3-11. Memory Layout Restrictions (See Figure 3-16 and Figure 3-17) Signal Intel740™ to SGRAM Stub SGRAM Stub MA[11:0] .25’’ 4.9” 0.25" 0.6” MD[63:0], DQM[7:0] .25’’ 3.9” 0.25" 0.4” Figure 3-16. Layout Dimensions (MA[11:0]) SGRAM 0.25"...

  • Page 78: Layout Dimensions (Wea#, Srasa#, Scasa#, Csa0#)

    3 Device AGP MotherBoard Design Figure 3-18. Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#) SGRAM 0.25" - 0.6" Intel740™ Chip 2.25" - 4.9" 0.25" - 0.6" SGRAM Table 3-13. Memory Layout Restrictions (See Figure 3-19) Signal Intel740™ to Resistor Resistor to SGRAM Stub SGRAM Stub TCLK1 0.6”...

  • Page 79: Device Agp Intel740™ Graphics Accelerator Memory Configurations

    3 Device AGP MotherBoard Design Figure 3-20. Memory Layout Dimensions (RCLK and OCLK to RCLK) Intel740™ Chip 1.0 ±0.25" OCLK 3.0 ±0.25" RCLK0 3.0 ±0.25" RCLK1 3.2.4.1 3 Device AGP Intel740™ Graphics Accelerator Memory Configurations In the following discussion the term row refers to a set of memory devices that are simultaneously selected by an SRAS and the CS# signal.

  • Page 80: Device Agp Motherboard Reference Design Schematics

    Several vendors offer components that can be used in this design. This page also shows the In Target Probe (ITP) Connector. The ITP connector is recommended in order to use the In Target Probe tool available from Intel and other tool vendors for Pentium II processor based platform debug.
  • Page 81 3 Device AGP MotherBoard Design 82443BX Component (PCI and AGP Interfaces) This page shows the 82443BX component, PCI and AGP Interfaces. The definition of pin AF3 has been changed from SUSCLK to BX-PWROK. Like PIIX4E PWROK, it is connected to the PWROK logic from the Power Connector page (P-26).
  • Page 82 6-pin optional ATX connector, and the Wake-On-LAN header. Note: A CPU Fan Header is required for the Intel Boxed Pentium II processor. The dual-color LED circuit is also used to reduce the voltage going to the power supply fan, thus decreasing its speed and quieting the system.
  • Page 83 3 Device AGP MotherBoard Design packs to as short of a trace as possible before routing to the V plane. If the V plane is on an inner layer, keep the trace distance to the via as short as possible by placing the via between pins 6 and 7 for each resistor package.

  • Page 84: 512Kx32 And 256Kx32 Pinout Compatibility

    This page show the logic needed to put the Intel 740 graphics accelerator into a low power state when a video add-in card is installed into the system. In low power mode, the Intel 740 chip is disabled and will not initiate or respond to cycles on the AGP bus.
  • Page 85 3 Device AGP MotherBoard Design DDC/I P-39 This page details the 3.3 volt/5 volt signal conversion as well as the DDC/I C connections. To perform the voltage translation, quick switches are used. Voltage Regulator P-40 This page shows the circuitry to convert from 3.3 Volts to 2.7 Volts. The regulator used in the reference design does not need any heatsink for the FET.
  • Page 86 3 Device AGP MotherBoard Design Intel740™ Graphics Accelerator Design Guide 3-28...
  • Page 87 I 2 C is a two-wire communications bus/protocol developed SERIAL/FLOPPY by Philips. SMBus is a subset of the I 2 C bus/protocol and was developed by Intel. Implementations of the I 2 C KEYBOARD/MOUSE bus/protocol or the SMBus bus/protocol may require...
  • Page 88 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT CK100 DESCHUTES BEEN VERIFIED FOR MANUFACTURING AN END USER & PRODUCT. iNTEL IS NOT RESPONSIBLE FOR THE MISUSE PROCESSOR VTT GEN. ITP CON. OF THIS INFORMATION. (SLOT 1) PG. 25 PG. 5 PG. 3,4...
  • Page 89 D#[3] HD#1 VCC_CORE D#[1] SLOT1_0.8 SLOT 1a 8,27 HD#[63:0] INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 * Please place as close to the connector as possible Title SLOT 1 (PART I) Size Document Number...
  • Page 90 R219-223 must VID1 be removed. RP19D SEL_VID2 VID2 RP20B SEL_VID3 VID3 SEL_VID4 RP20D VID4 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title SLOT 1 (PART II) Size Document Number Custom 3 DEVICE AGP Date: 22:16:57...
  • Page 91 DBRESET# TDI 3 ITP_PON TDO 3 TRST# 3 ITPREQ# 3 PRDY0_R# PRDY#0 3,27 ITPCLK ITP CONN INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title CLOCK SYNTHESIZER Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 92 **Locate "T" and cap close to BX. 3,9,10,11,13,28,33 SMBDATA ** Please make DCLKREF trace length equal to 2.5" more INTEL CORPORATION than the DCLK outputs to the DIMMs. DCLK outputs to GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 *The unused SDRAM the DIMMs should all be the same recommended length.
  • Page 93 SBSTB 15,28,34 C182 .1uF AGPREFV C204 ** Place as close to 0.001uF 443BX as possible. 443BX_10 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title 82443BX PCI AND AGP INTERFACES Size Document Number Custom 3 DEVICE AGP...
  • Page 94 MD62 HD#62 MD62 HD62# MD63 HD#63 MD63 HD63# GTLREF2 MECC0 GTLREF1 AE11 MECC0 MECC1 AA10 MECC1 INTEL CORPORATION MECC2 AA23 MECC2 MECC3 AA26 MECC3 GTLREFA GRAPHICS COMPONENTS DIVISION MECC4 AF11 MECC4 GTLREFB 1900 PRAIRIE CITY RD. FM5-79 MECC5 AD12 MECC5...

  • Page 95: Dimm Socket

    DCLK9 DCLK10 DCLK11 CONTROL B CONTROL A 443BX DCLK[11:0] 6,10,11 DIMM REF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Block diagram for 3 DIMM MA and control connection. Title DIMM SOCKET 0 Size Document Number...
  • Page 96 /WE0 SCAS_A# 6,9 /CAS SRAS_A# 6,9 /RAS DCLK4 DCLK5 DCLK6 DCLK7 DCLK[11:0] 6,9,11 DIMM REF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title DIMM SOCKET 1 Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 97 /WE0 /CAS SCAS_B# 6 /RAS SRAS_B# 6 DCLK0 DCLK1 DCLK2 DCLK3 DCLK[11:0] 6,9,10 DIMM REF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title DIMM SOCKET 2 Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 98 PDD13 IOW# 14,18,29,33 PDD13 IOW# PDD14 IOCHRDY 14,18,29 PDD14 IOCHRDY PDD15 AEN 14,18 PDD15 INTEL CORPORATION PDD[15:0] GRAPHICS COMPONENTS DIVISION PIIX4_15 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title PIIX4E (PART I) Size Document Number Custom 3 DEVICE AGP...
  • Page 99 74HC112 R158 RSMRST# PX4_CFG1 28 0.1 uF CONFIG1 U35E JK_CLR 48Mhz_0 48Mhz CONFIG2 PX4_CFG2 28 3VSB OSC2 INTEL CORPORATION PXPCLK PCICLK GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 74LVC14 R239 C375 R218 FOLSOM, CA 95630 0.01uF 8.2K Title 32.768KHz...
  • Page 100 RP100D 8.2K RP100B 8.2K 8.2K RP100C 21,33 XD[7:0] XOE# ROMCS# XDIR# ROMDIR# INTEL CORPORATION KBLOCK# 26 FDC37C932FR_1.3 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 R114 ULTRA I/O FOLSOM, CA 95630 Stuff for 93XFR Title I/O CONTROLLER (ULTRA I/O) Size...
  • Page 101 GAD6 GAD5 GAD4 GAD3 GAD2 Vddq3.3 Vddq3.3 GAD1 GAD0 RESERVED RESERVED AGP_CONN_1.3 INTEL CORPORATION 7,34 GAD[31:0] GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 GC/BE#[3:0] FOLSOM, CA 95630 Title ACCELERATED GRAPHICS PORT (AGP) CONNECTOR Size Document Number Custom 3 DEVICE AGP...
  • Page 102 RP68C AD27 R_AD27 PU2_ACK64# 5.6K 0.1 uF RP68D 2.7K PU2_REQ64# PRSNT#22 2.7K INTEL CORPORATION 0.1 uF GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title PCI CONNECTORS 1 & 2 Size Document Number Custom 3 DEVICE AGP...
  • Page 103 RP60 AD29 R_AD29 SDONEP3 0.1 uF RP69A 2.7K SBOP3 PU3_REQ64# 2.7K 5.6K INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title PCI CONNECTORS 3 & 4 Size Document Number Custom 3 DEVICE AGP Date: 22:16:57...
  • Page 104 SD12 12,29 SD13 12,29 SD13 RMASTER# SD14 12,29 MASTER# SD14 SD15 SD15 12,29 CON_ISA16C ISA 0 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title ISA SLOTS Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 105 SECONDARY R137 R129 IDE CONN. 13,14,18,29 IRQ14 IDE CONN. 13,14,18,29 IRQ15 R165 R231 5.6K INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title PCI IDE CONNECTORS Size Document Number Custom 3 DEVICE AGP Date: 22:16:57...

  • Page 106: Usb Connectors

    DO NOT PIIX4. STUFF R112 R_USBD1- USBAGP- 15 NOTE: USE PIIX4 APPLICATION NOTE FOR LAYOUT GUIDELINES INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title USB HEADER Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 107 12,18,29 MEMR# FL_VPP FL2MPU FL1MPU E28F002BC-T TSOP SOCKET C396 0.1 uF C395 0.1 uF BIOSCS# INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title SYSTEM ROM Size Document Number Custom 3 DEVICE AGP Date: 15:23:35...
  • Page 108 180pF RP85 STB#R AFD#R CP4B SLIN#R 180pF INIT#R CP4A 180pF ACK# BUSY SLCT ERR# INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title PARALLEL PORT Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 109 PIIX4 for BIOS detection of a DSKCHG# floppy drive. SIDE1# RDATA# WPT# TRK0# WGATE# WDATA# STEP# DIR# MOTEB# INTEL CORPORATION DRVSA# DRVSB# GRAPHICS COMPONENTS DIVISION MOTEA# 1900 PRAIRIE CITY RD. FM5-79 INDEX# FOLSOM, CA 95630 DRATE0 TP094 TP92 Title REDWC#...
  • Page 110 MSCLK_FB# MSCLK_FB# TP098 TP093 MSCLK# FBHS01K KBSHGND 470pf 470pF 470pF 470pF FBHS01K 470pF FBHS04B INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title KEYBOARD/MOUSE INTERFACE Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 111 R246 100uF 10V LT1575_0.1 (Solid Tantalum) R240 C230 C379 V25_R3 C376 C365 1.0 uF 1.0 uF INTEL CORPORATION 22 uF 10V 1.30K 1 uF CERAMIC GRAPHICS COMPONENTS DIVISION R220 C412 C413 1900 PRAIRIE CITY RD. FM5-79 1.21K 2200pF 0.01 uF...
  • Page 112 74LVC14 0.01 uF 22uF R204 R_RSMRST# SOT-23 C374 1.0 uF Resume Reset circuitry INTEL CORPORATION using a 22 msec delay GRAPHICS COMPONENTS DIVISION and Schmitt trigger 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 logic. Title Power Connector & Misc...
  • Page 113 HA#22 ADS# HA#28 56 ohm RS#[2:0] 56 ohm RP43 HA#31 HA#24 HA#26 NOTE : VTT = TERMINATION INTEL CORPORATION HA#30 VOLTAGE GRAPHICS COMPONENTS DIVISION 56 ohm 1900 PRAIRIE CITY RD. FM5-79 HA#29 FOLSOM, CA 95630 Title GTL TERMINATION Size Document Number...
  • Page 114 8.2K GPI16 7,15,34 SBSTB GPI17 8.2K GPI13 7,15,34 GPAR 100K 2.7K RP110 GPI7 INTEL CORPORATION 2.7K GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title Pullups; AGP/PCI/PIIX4 Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 115 M HOLE1 M HOLE1 M HOLE1 M HOLE1 LA18 12,18 SMEMW# LA17 12,18 SMEMR# SA19 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 12,18 LA[23:17] 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title ISA BUS PULLUPS Size Document Number Custom 3 DEVICE AGP...
  • Page 116 C113 0.01 uF C115 0.01 uF 0.01 uF C386 0.01 uF 0.01 uF INTEL CORPORATION 0.01 uF GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 C405 T i t l DRAM, CLOCK AND 440BX DECOUPLING CAPACITORS 0.01 uF 0.01 uF...
  • Page 117 C134 0.01 uF 0.01 uF 10uF 10uF C254 C188 0.01 uF 10uF C280 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title 3.3 VOLT AND BULK POWER DECOUPLING Size Document Number Custom 3 DEVICE AGP...
  • Page 118 C145 0.01 uF C128 0.01 uF 0.01 uF C199 C131 0.01 uF 0.01 uF C146 C196 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title TERMINATION DECOUPLING Size Document Number 3 DEVICE AGP Custom Date:...
  • Page 119 R185 R184 C388 C387 2.7K 66.5K 100K 80.6K 66.5K 0.1 uF 0.1 uF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA. 95630 Title LM79 MONITOR Size Document Number Custom 3 DEVICE AGP Date: Thursday, July 02, 1998...
  • Page 120 ADSTB_0 ADSTB-A 7,15,28 AGPREF C179 VMIHA2 AGPREF .01UF VMIHA3 VMIHA4 INTEL740 (A) INTEL740 CHIP INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title Intel740 Graphics Accelerator Part A Size Document Number Custom 3 DEVICE AGP...
  • Page 121 VCCDP LMD62 AA04 MD62 VCCAP LMD63 AF23 MD63 AF24 AF26 AF25 AE22 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION INTEL740 CHIP 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title Intel740 Graphics Accelerator Part B Size Document Number Custom 3 DEVICE AGP...
  • Page 122 VGA_HSYNC HSYNC 35 22PF 22PF VGA CONN VGA_VSYNC VSYNC 35 5VDDCCL BLUE 5VDDCCL 22PF 22PF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title VGA CONNECTOR Size Document Number Custom 3 DEVICE AGP Date: 22:16:57...
  • Page 123 LMD1 LMA2 LMD33 LMA1 LMD0 LMA1 LMD32 LMA0 LMA0 LMA[10:0] LMA[10:0] SGRAM 512Kx32 SGRAM 512Kx32 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title SGRAMS Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 124 SCASB# 35 SRASB# 35 12,18,33 SYSCLK CS0B# 35 CS1B# 35 VCC3 74LVT244_1 GPO28 Q_NAND INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title LOW POWER MODE LOGIC Size Document Number Custom 3 DEVICE AGP Date:...
  • Page 125 RP5B 2.2K QS3861 5VSCL 3VSCL 35 5VSDA 3VSDA 35 5VDDCDA 3VDDCDA 35 5VDDCCL 3VDDCCL 35 QS3861 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 126 C122 C121 .1UF .01UF 22UF 10UF .1UF .1UF .01UF .01UF .1UF .1UF .01UF .01UF INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title VOLTAGE REGULATOR Size Document Number Custom 3 DEVICE AGP Date: 22:16:57 Sheet...
  • Page 127 REVISION1.0 8/98 First release of 3 Device AGP schematics. INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 Title REVISION HISTORY Size Document Number Custom 3 DEVICE AGP 22:16:57 Date: Sheet...

  • Page 128: Thermal Considerations

    Thermal Considerations...

  • Page 130: Thermal Design Considerations Chart

    Thermal Considerations Thermal Considerations Thermal design is an important step in the total design process which must not be overlooked. Systems or cards designed without considering the thermal environment may experience failures. Depending on the usage of the Intel740™ graphics accelerator, the thermal solution may change.
  • Page 131 Thermal Considerations Intel740™ Graphics Accelerator Design Guide...

  • Page 132: Mechanical Information

    Mechanical Information...

  • Page 134: Board Dimensions

    Intel has enabled. The mounting holes must be nonplated but each must have a grounded annular ring on the solder side of the board surrounding the hole. This annular ring should have an inner diameter of 150 mils and an outer diameter of 300 mils.

  • Page 135: Vmi Header Placement

    Mechanical Information VMI Header Placement The VMI header allows the connection of a DVD daughter Card. The reference card places the header at the bottom of the card. For other designs, these headers may be placed at the top of the board.

  • Page 136: Pin Video Connector

    Mechanical Information The dimensions shown in Figure 5-3 should be kept in mind when placing the VMI Headers. The reference DVD daughter cards will be designed for a maximum graphics board component height of 0.2”. If the component height exceeds these dimensions underneath the daughter card, the daughter card may not fit.

  • Page 137: Bracket

    Mechanical Information Bracket Figure 5-5. Recommended Bracket Placement Figure 5-6. Recommended Bracket Cutout Intel740™ Graphics Accelerator Design Guide...

  • Page 138: Nlx Considerations

    Mechanical Information NLX Considerations The NLX card has a special bracket design and card cutout to accommodate the NLX chassis. The NLX card can be used in an ATX chassis, but needs to use an ATX bracket. Unless a dual sided board is used, the full featured reference design will not be feasible on the NLX add-in card.
  • Page 139 Mechanical Information Intel740™ Graphics Accelerator Design Guide...

  • Page 140: Third Party Vendors

    Third Party Vendors...

  • Page 142: Voltage Regulator

    Sanyo Denki* — James Sia (310) 212-7724 — Fan/Heatsink P/N 109P4405H9026 — Clip, prototype XF-8300 — Clip, production 109-688 Flash Components • Intel — 28F010 — 28F001 Video Encoders/Decoders • Rockwell* Semiconductor — Tim Yates (619) 535-3522 — Video Encoder (Bt868/869) —...

  • Page 143: Dvd Daughter Cards

    Third Party Vendors DVD Daughter Cards Intel has worked to enable a variety of hardware DVD solutions. Each of the vendors below will have a functional reference daughter card compatible with the Intel740™ graphics accelerator reference design. These designs can be modified so that the DVD component is down on the card or left as is so that multiple DVD solutions can be implemented.
  • Page 144 Application Notes...
  • Page 145 Intel740™ Graphics Accelerator Application Note 653: Thermal Design Considerations April 1998 Order Number: 292211-002...

  • Page 146: Application Note 653: Thermal Design Considerations

    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
  • Page 147 Contents Introduction ........................1 Document Goals ....................1 Importance of Thermal Management............... 1 Intel740™ Graphics Accelerator Packaging Terminology ....... 2 Thermal Specifications....................3 Case Temperature ................... 3 Power....................... 4 Designing for Thermal Performance ................5 Airflow Management ..................5 Cooling Solutions ......................7 System Fans ....................
  • Page 148 Figures Example of air exchange through a PC chassis ..........6 Fan Placement and Layout of an ATX Form Factor Chassis - Top View ..8 Fan Placement and Layout of an NLX Form Factor Chassis - Top View ..8 Low Profile Fan Heat Sink Drawing ...............

  • Page 149: Introduction

    Introduction In a system environment, the chipset temperature is a function of both the system and component thermal characteristics. The system level thermal constraints consist of the local ambient temperature at the component, the airflow over the component and surrounding board as well as the physical constraints at, above, and surrounding the component.

  • Page 150: Intel740™ Graphics Accelerator Packaging Terminology

    Intel740™ Graphics Accelerator Thermal Design Considerations Intel740™ Graphics Accelerator Packaging Terminology Ball Grid Array. A package type defined by a resin-fiber substrate on which a die is mounted, bonded and encapsulated in molding compound. The primary electrical interface is an array of solder balls attached to the substrate opposite the die and molding compound.

  • Page 151: Thermal Specifications

    Intel740™ Graphics Accelerator Thermal Design Considerations Thermal Specifications The Intel740™ graphics accelerator power dissipation can be found in the Intel740™ Graphics Accelerator Datasheet and Intel740™ Graphics Accelerator Specification Updates. Please refer to these documents to verify the actual thermal specifications for the Intel740 graphics accelerator. In general, systems should be designed to dissipate the highest possible thermal power.

  • Page 152: Power

    Intel740™ Graphics Accelerator Thermal Design Considerations Power In previous generations of graphics accelerators where Quad Flat Pack (QFP) packages have been the primary package type, the majority of power dissipation has been through the plastic case of the package into the surrounding air. With the advent of Ball Grid Array (BGA) packaging for graphics accelerators, the majority of the thermal power dissipated by the chipset typically flows into the motherboard where it is mounted.

  • Page 153: Designing For Thermal Performance

    Intel740™ Graphics Accelerator Thermal Design Considerations Designing for Thermal Performance In designing for thermal performance, the goal is to keep the component within the operational thermal specifications. The heat generated by the components within the chassis must be removed to provide an adequate operating environment for all of the system components. To do so requires moving air through the chassis to transport the heat generated out of the chassis.
  • Page 154 Intel740™ Graphics Accelerator Thermal Design Considerations Figure 1. Example of air exchange through a PC chassis Fan (intake) Fan (exhaust) Cards Cards Little Power Power Airflow or Supply Supply Recirculated Drive Drive Vent Fan (intake) Poor Air Exchange Good Air Exchange Application Note 653...

  • Page 155: Cooling Solutions

    Intel740™ Graphics Accelerator Thermal Design Considerations Cooling Solutions Numerous alternatives for cooling solutions exist for the Intel740 graphics accelerator. This section will explore system cooling solutions as well as package heat-sinks. Due to their varying attributes, each of these solutions may be appropriate for a particular system implementation. System Fans Fans are needed to move the air through the chassis.
  • Page 156 Intel740™ Graphics Accelerator Thermal Design Considerations Figure 2. Fan Placement and Layout of an ATX Form Factor Chassis - Top View Passive SECC Exhaust Slot PCI Slot Power Supply Motherboard ISA Slot Peripherals Vent Required Fan > Power Supply Fan Figure 3.

  • Page 157: Fan Direction

    Intel740™ Graphics Accelerator Thermal Design Considerations 4.1.2 Fan Direction If the fan(s) are not moving air across the graphics processor and the card then little cooling can occur. Hence, the Intel740 graphics accelerator may exceed it’s absolute maximum thermal ratings. Note the recommended fan airflow directions in Figure 2 Figure...

  • Page 158: Vent Shape

    Intel740™ Graphics Accelerator Thermal Design Considerations 4.1.5.2 Vent Shape Round, staggered pattern openings are best for EMI containment, acoustics and airflow balance. For material related to EMI considerations please see the Pentium II Processor EMI Design Guidelines Application Note. 4.1.6 Ducting Ducts can be designed to isolate components from the effects of system heating and to maximize the thermal budget.

  • Page 159: Low Profile Fan Heat Sink

    Intel740™ Graphics Accelerator Thermal Design Considerations 4.2.2 Low Profile Fan Heat Sink A generic drawing for this Fan Heat Sink is shown in Figure 4. Recommended sources for the Low Profile Fan Heat Sink are discussed in Appendix A, “Sources”. The thermal performance of the Fan Heat Sink and Thermal Interface Material (combined) must be sufficient to maintain a case temperature at or below T (See...

  • Page 160: Low Profile Fan Heat Sink Electrical Requirements

    Intel740™ Graphics Accelerator Thermal Design Considerations Figure 5. PCB Layout Guidelines for Mounting Holes 4.2.2.2 Low Profile Fan Heat Sink Electrical Requirements The Fan Heat Sink’s total maximum power usage should not exceed 1 Watt and should start and operate within ±10% of rated voltage. The Fan Heat Sink may use a connector which incorporates 2 separate connections: 12 Volt power, ground and signal (tachometer function).

  • Page 161: Low Profile Fan Heat Sink Attach

    Intel740™ Graphics Accelerator Thermal Design Considerations Figure 6. Fan Heat Sink Connector Design 4.2.2.3 Low Profile Fan Heat Sink Attach The Low Profile Fan Heat Sink uses a mechanical attach to the card in conjunction with a thermal interface material. The recommended process flow for attaching the Low Profile Fan Heat Sink is shown as follows: 1.

  • Page 162: Low Profile Passive Heat Sink

    Intel740™ Graphics Accelerator Thermal Design Considerations Table 2. Default Thermal Solution Reliability Validation 85% relative humidity Visual Check Humidity 55 °C, 1000 hours RPM Check Visual Check 7,500 on/off cycles with each cycle specified as 3 minutes Power Cycling on, 2 minutes off 70 °C RPM Check NOTES: 1.

  • Page 163: Tape Attach

    Intel740™ Graphics Accelerator Thermal Design Considerations 5. Join and secure the assembly centering the heat sink on the component. Wait for the adhesive to fixture (approximately 5 minutes) before any further handling. Full cure occurs in 4-24 hours. Note: The successful application of this product depends on accurate dispensing on to the parts being bonded.
  • Page 164 Intel740™ Graphics Accelerator Thermal Design Considerations Figure 9. Completing the Attach Process Note: Silicone Adhesive always joins to either the heat sink or the moldcap, the Acrylic Adhesive sides must join to each other (Figure Note: As every motherboard, system and heat sink combination may introduce variance in attach strength, it is generally recommended that the user carefully evaluate the reliability of tape attaches prior to using in high volume.

  • Page 165: Reliability

    Intel740™ Graphics Accelerator Thermal Design Considerations Table 3. Tape Attach Application Temperature/Pressure Option Pressure Temperature Time 10 psi (0.069 mPa) 22°C 15 seconds 30 psi (0.207 mPa) 22°C 5 seconds 10 psi (0.069 mPa) 50-65°C 5 seconds 30 psi (0.207 mPa) 50-65°C 3 seconds NOTE: Approximately 70% of the ultimate adhesion bond strength is achieved with initial application, 80-90% of...

  • Page 166: Bond Line Management

    Intel740™ Graphics Accelerator Thermal Design Considerations 4.3.1 Bond Line Management The gap between the mold-cap and the heat sink base will impact heat-sink solution performance. The larger the gap between the two surfaces, the greater the thermal resistance. The thickness of the gap is determined by the flatness of both the heat sink base and the mold-cap, plus the thickness of the thermal interface material (e.g., PSA, thermal grease, epoxy) used between these two surfaces.

  • Page 167: Measurements For Thermal Specifications

    Intel740™ Graphics Accelerator Thermal Design Considerations Measurements for Thermal Specifications To appropriately determine the thermal properties of the system, measurements must be made. Guidelines have been established for the proper techniques to be used when measuring the Intel740 graphics accelerator case temperatures. Section 5.1, “Case Temperature Measurements”...

  • Page 168: Power Simulation Software

    However, it is conceivable that new applications and drivers will be written which take advantage of this increased bandwidth. To ensure the thermal performance of the Intel740 graphics accelerator while running future applications, Intel has developed a software utility which emulates this anticipated power dissipation.
  • Page 169 Intel740™ Graphics Accelerator Thermal Design Considerations Figure 12.Thermal Enhancement Decision Flowchart Start Select Heat Sink. Attach Intel740 graphics (See Section 4.2) accelerator to the motherboard process using your normal reflow Attach Thermocouples as Attach Thermocouples as described in Section 5.1. described in Section 5.1.

  • Page 170: Conclusion

    Intel740™ Graphics Accelerator Thermal Design Considerations Conclusion As the complexity of today’s graphics accelerators continues to increase, so do the power dissipation requirements. Care must be taken to ensure that the additional power is properly dissipated. Heat can be dissipated using improved system cooling, selective use of ducting and/or passive heat sinks.

  • Page 171: Sources

    Appendix A Sources Low Profile Fan Heat Sink Sales Locations Sanyo Denki Please visit WEB at http://www.sanyodenki.co.jp/profile_e17.html Future Second Source Panasonic Part Numbers Sanyo Denki 109P4405H9026 Low Profile Passive Heat Sink Sales Locations Thermalloy please visit WEB at: http://www.thermalloy.com please visit WEB at: http://www.jme.com Part Numbers Thermalloy...
  • Page 172 Intel740™ Graphics Accelerator Thermal Design Considerations Application Note 653...
  • Page 173 04565-001-Sao Paulo, SP Brazil Tel: 55-11-5505-2296 FOR MORE INFORMATION To learn more about Intel Corporation visit our site on the World Wide Web at http://www.intel.com/ * Other brands and names are the property of their respective owners. Printed in USA/0498/PSA...
  • Page 175 Intel740™ Graphics Accelerator Application Note: 3 Device AGP System BIOS Design Guidelines August 1998 Order Number: 290628-001...
  • Page 176 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
  • Page 177 Contents Introduction ........................1 Low Power Mode Overview ..................1 State Diagrams ....................2 Supported Single Monitor and Mulitmonitor Configurations......4 Software Sequence..................4 Figures Schematic Diagram for GPO27 ..............2 Schematic Diagram for GPO28 ............... 2 Intel740™ Graphics Controller (On-board Device) Remains in Low Power Mode .....................

  • Page 179: Introduction

    Introduction For the 3 Device AGP down motherboard design discussed in the Intel740™ Graphics Accelerator Design Guide, Rev 3 (order number 290619), both the video BIOS and support for the 3 Device AGP low power logic must be integrated into the system BIOS. This document details the needed changes to system BIOS to implement the low power logic.

  • Page 180: State Diagrams

    Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines Figure 1. Schematic Diagram for GPO27# Vcc3 4.7 KΩ GPO27# PIIX4E RESET Intel740™ PCIRST# Vcc3 Chip 4.7 KΩ ROMA16 OUT1 PCICLK3 Figure 2. Schematic Diagram for GPO28# Vcc3 Vcc3 2.2 KΩ TEST OUT1 WEB#...
  • Page 181 Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines Figure 3. Intel740™ Graphics Controller (On-board Device) Remains in Low Power Mode System Reset Low Power Mode Figure 4. Intel740™ Graphics Controller (On-board Device) State Diagram System Reset Low Power Mode Functional Mode...

  • Page 182: Supported Single Monitor And Mulitmonitor Configurations

    Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines Supported Single Monitor and Mulitmonitor Configurations Table 2. Monitor and Mulitmonitor Configurations Configuration Single Monitor Multimonitor On-Board Primary Graphics AGP Add-in Non AGP Non AGP Non AGP Non AGP Intel740™ Device Card (PCI or ISA)
  • Page 184 South America Intel Semicondutores do Brazil Rua Florida 1703-2 and CJ22 CEP 04565-001 Sao Paulo-SP Brazil Phone: (55) 11 5505 2296 For More Information To learn more about Intel Corporation, visit our site on the World Wide Web at www.intel.com...
  • Page 185 Reference Information...
  • Page 187 PC SGRAM Specification Revision 0.9 February 1998 Order Number: Not Applicable...
  • Page 188 NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
  • Page 189 Contents Introduction ........................1 Objective ......................1 Scope of This Document.................. 1 Convention Used ..................... 1 Pinout..........................2 Pin Functional Descriptions (Simplified) ............4 Control Registers ......................5 Mode Register and Modes Required to be Supported........5 Special Mode Register..................5 Color Register ....................
  • Page 190 SGRAM AC/DC Parameters..................21 DC Specifications for 100-166 MHz............... 21 A.C. Specifications for 100-166 MHz ............. 21 A.C. Timing Parameters for 100-166 MHz............. 22 DC Specifications for 166-250 MHz............... 23 A.C. Specifications for 166-250 MHz ............. 23 A.C. Timing Parameters for 166-250 MHz............. 23 IBIS: I/V Characteristics for Input and Output Buffers ........

  • Page 191: Introduction

    Introduction Objective The objective of this document is to define a SGRAM specification (“PC SGRAM”). It should be easy to design and manufacture and highly cost optimized for the main stream volume desktop Graphics architecture PCs. Scope of This Document The scope of this document is limited to identify and define all the essential functionality that is needed to be implemented for “PC SGRAM”.

  • Page 192: Pinout

    PC SGRAM Specification Pinout The pinout for 8Mb and 16Mb SGRAM configurations are shown below. Figure 1. 256kx32 SGRAM Pinout DQ29 VssQ DQ30 DQ31 100 pin PQFP package Dimension: 14mm x 20mm x 1.4mm VssQ Revision 0.9...
  • Page 193 PC SGRAM Specification Figure 2. 512kx32 SGRAM Pinout DQ29 VssQ DQ30 DQ31 100 pin TQFP package Dimension: 14mm x 20mm x 1.4mm VssQ Revision 0.9...

  • Page 194: Pin Functional Descriptions (Simplified)

    PC SGRAM Specification Pin Functional Descriptions (Simplified) Table 1. Pin Functional Description Symbol Type Description A[9:0] Input - Synchronous Address. Multiplexed Row and Column Address. Input - Synchronous Bank Address. BA0 and BA1 specify the selected Bank during Input - Synchronous Auto Precharge (Multiplexed with Row Address).

  • Page 195: Control Registers

    PC SGRAM Specification Control Registers Mode Register and Modes Required to be Supported PC SGRAM’s mode register is accessed through the Mode Register Write command. The Mode Register is used to load the value of CAS Latency, Burst Type, & Burst Length Table 2.

  • Page 196: Color Register

    PC SGRAM Specification Color Register Data is loaded into the Color Register through the Special Mode Register Write command. During the execution of the Special Mode Register Command, bit A[6] is used to determine if a new value is to be loaded into the Mask registers. If A[6] =1 during the special mode register command, then the value on DQ[31:0] is loaded into the Color Register.

  • Page 197: Command Truth Table

    PC SGRAM Specification Command Truth Table Table 5. Command Truth Table Function Symbol Command & Address BA0, RAS# CAS# A[7:0] Data for Mode Register Mode Write Register. Special Mode Data for SMRWR Register Write CBR Refresh Activate (Single Bank Bank) Address Address Column...

  • Page 198: Operative Command Table

    PC SGRAM Specification Operative Command Table Table 7. Operative Command Table Current RAS# CAS# Address Command Action Notes state Nop or Power Idle DSEL Down Nop or Power Down BA,CA, READ/ ILLEGAL A8/A9 READAP BA,CA, WRITE/ ILLEGAL A8/A9 WRITEAP BA,CA BLKWR ILLEGAL BA,RA...
  • Page 199 PC SGRAM Specification Table 7. Operative Command Table Current RAS# CAS# Address Command Action Notes state Term burst, BA,A8 PRE/PALL precharge Term burst CBR/SELF ILLEGAL Opcode ILLEGAL Opcode SMRWR ILLEGAL Continue burst WRITE DSEL to end ->Write recovering Continue burst to end ->...
  • Page 200 PC SGRAM Specification Table 7. Operative Command Table Current RAS# CAS# Address Command Action Notes state Continue bust to end-> Write recovering with auto precharge BA,CA, READ/ ILLEGAL A8/A9 READAP BA,CA, WRIT/ ILLEGAL A8/A9 WRITEAP BA,CA BLKWR ILLEGAL BA,RA ILLEGAL 4,13 BA,A8 PRE/PALL...
  • Page 201 PC SGRAM Specification Table 7. Operative Command Table Current RAS# CAS# Address Command Action Notes state NOP - Enter Write DSEL row active Recovering after Tdpl NOP - Enter row active after Tdpl BA,CA, READ/ Start Read, A8/A9 READAP optional AP BA,CA, WRIT/ New Write,...
  • Page 202 PC SGRAM Specification Table 7. Operative Command Table Current RAS# CAS# Address Command Action Notes state Mode NOP - Enter Register DSEL idle after tmrd accessing NOP - Enter idle after tmrd READ/ WRITE/ READAP/ ILLEGAL WRITEAP/ BLKWR ILLEGAL ACT/PRE/ PALL/ CBR/ ILLEGAL SELF/MRS/...

  • Page 203: Row/Column Addressing Per Memory Size/# Banks

    PC SGRAM Specification Row/Column Addressing Per Memory Size/# Banks Table 8. Row, Column and Bank addressing Parameter 2x128kx32 (8Mb) 2x256kx32 (16Mb) Bank Address Row Address A[8:0] A[9:0] Column Address A[7:0] A[7:0] Auto-Precharge Page Size 256x32 256x32 Revision 0.9...

  • Page 204: Functional Description

    PC SGRAM Specification Functional Description Power Up Sequence The SGRAM should be initialized by the following sequence of operations: • Clock will be applied at power up along with power (clock frequency will be unknown). • The clock will be stabilized within 100usec after power stabilizes. •...

  • Page 205: Precharge Selected Bank

    PC SGRAM Specification Precharge Selected Bank The precharge operation should be performed on the active bank when precharge selected bank command is issued. When the precharge command is issued with address A8/A9 low, BA selects the bank to be precharged. At the end of the precharge selected bank command the selected bank should be in idle state after the minimum T is met.

  • Page 206: Block Write

    PC SGRAM Specification Block Write The Block Write command is used to write a block of data to an active row and bank within the device. The Block Write command is issued by driving CS# low, RAS# high, CAS# low, WE# low and DSF high.

  • Page 207: Power Down Mode

    PC SGRAM Specification 7.10 Power Down Mode The Power down mode for PC SGRAM can be entered when both banks are in idle state (precharged) and CKE is asserted low. When in power down mode all input and output buffers are de-activated (except for CKE).

  • Page 208: Essential Functionality For The "Pc Sgram" Device

    PC SGRAM Specification Essential Functionality for the “PC SGRAM” device The functionality that are essential for the “PC SGRAM” device are described below: • Burst Read • Burst Write • Multi bank access • Burst Read with Autoprecharge • Burst Write with Autoprecharge •...

  • Page 209: Precharge Termination Of A Burst Read

    PC SGRAM Specification 8.3.1.1 Precharge Termination of a Burst Read Burst Read (with no autoprecharge) can be terminated earlier using a precharge command along with the DQM. This terminates reads when the remaining data elements are not needed. It allows starting the precharge early.

  • Page 210: Back To Back Command Support

    PC SGRAM Specification Back to Back Command Support Minimum command to command delay of 1 Clock should be supported. Auto Refresh (CBR) Command An auto refresh (CBR) should be used to refresh the SGRAM array explicitly. Refresh addresses should be generated internally by the SGRAM device and incremented after each auto refresh automatically.

  • Page 211: Sgram Ac/Dc Parameters

    PC SGRAM Specification SGRAM AC/DC Parameters DC Specifications for 100-166 MHz Table 9. Absolute Maximum D.C. Rating Symbol Parameter Units Notes Vin, Vout Voltage on any pin w.r.t V SS -0.5 V DD + 0.5 V DD , V DDQ Voltage Supply pins pin w.r.t V SS -0.5 °C Storage Temperature...

  • Page 212: A.c. Timing Parameters For 100-166 Mhz

    PC SGRAM Specification Table 12. Refresh Rate Symbol Parameter Units Notes Tref Refresh rate / row 15.6 usec NOTE: 1. The overall array refresh is determined by multiplying the specified row refresh rate by the number of rows in the total array. A.C.

  • Page 213: Dc Specifications For 166-250 Mhz

    PC SGRAM Specification DC Specifications for 166-250 MHz Absolute Maximum D.C. Rating (TBD) D.C Operating Requirements (TBD) A.C. Specifications for 166-250 MHz Maximum AC Operating Requirements (TBD) Refresh Rate (TBD) A.C. Timing Parameters for 166-250 MHz Table 14. 166, 200, 250 MHz & 166 MHz AC Timing Parameters Parameter Symbol Min Max...

  • Page 214: Ibis: I/V Characteristics For Input And Output Buffers

    PC SGRAM Specification IBIS: I/V Characteristics for Input and Output Buffers (TBD) Figure 6. A.C Timing Parameters <---------------- tcyc -------------> <-----tch------><-------tcl------> |<----tsi---><---thi--->| Inputs <---------tohz------>| <---toh--> <------ tac ------>| <----toh--->| outputs ac_tim.td A.C Timing Parameters NOTE: 1. Reference level is set at 1.5V, AC measurements are specified into 50pf load. 2.

  • Page 215: Ibis Reference

    PC SGRAM Specification IBIS Reference The IBIS Open Forum is an industry-wide forum that controls the official IBIS specification. Minutes of IBIS meetings, email correspondence, proposals for specification changes, etc. are on- line at "vhdl.org". To join in the email discussions, send a message to "ibis-request@vhdl.org" and request that your name be added to the IBIS mail reflector.
  • Page 216 PC SGRAM Specification Revision 0.9...
  • Page 217 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics 64-bit (Non-ECC/Parity) 144-pin Module Revision 0.91 February 1998 Order Number: Not Applicable...
  • Page 218 NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
  • Page 219 Contents Unbuffered Graphics SO-DIMM Module ............... 1 General Features ..................... 1 Labeling ......................1 Mechanical Outline ....................... 2 Environmental Requirements..................3 Pin Assignments ......................4 Graphics SO-DIMM Block Diagram ................5 Address Translation ...................... 9 Configuration....................9 Default Parameters ..................10 Resistor Strapping Options ................11 6.3.1 Clock Frequency and Memory Timing ..........11...
  • Page 220 Figures SDRAM SO-DIMM Module ................2 256K/512 x 64 SGRAM SO-DIMM Block Diagram (1 bank of two 256K/512K x 32) ..............5 512K/1M x 64 SGRAM SO-DIMM Block Diagram (2 banks of two 256K/512K x 32)..............6 256K/512K x 32 SGRAM SO-DIMM Block Diagram (1 bank of one 256K/512K x 32) ..............

  • Page 221: Unbuffered Graphics So-Dimm Module

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Unbuffered Graphics SO-DIMM Module General Features • 144-pin, small-outline, dual-in-line memory module (SO-DIMM). • 64-bit data bus (non-ECC/Parity) • Maximum of 8MB per module with extensions to 32MB • SDRAM/SGRAM • Single, 3.3V ±10% power supply •...

  • Page 222: Mechanical Outline

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Mechanical Outline • Dimensions: 67.6 mm (length) X 25.4-50.8 mm (height) X 1.0 mm (thickness) • 144-pin (0.8 mm pitch zig-zag) For mechanical specifications of SO-DIMM modules, refer to the JEDEC Committee Ballot JC-42.5-95-171 144-pin SDRAM SO-DIMM Item 708.4 (herein referred to as the JEDEC SO-DIMM specification).

  • Page 223: Environmental Requirements

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Environmental Requirements Table 1. Environmental Requirements Operating Temperature C to +65 Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 10.106 PSI (up to 10,000 ft.) Storage Temperature C to +70 Storage Humidity 5% to 95% without condensation Storage Pressure 1.682 PSI (up to 50,000 ft.) at 50...

  • Page 224: Pin Assignments

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Pin Assignments Table 2. SO-DIMM Module Pin Assignments PIN # Front PIN # Back PIN # Front PIN # Back CLK1 CLK0 DQ63 DQ62 DQ61 DQ60 RSVD RSVD DQ59 DQ58 RSVD (A11) DQ57 DQ56 DQ55 DQ54 DQ53...

  • Page 225: Graphics So-Dimm Block Diagram

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Graphics SO-DIMM Block Diagram Figure 2 through Figure 5 illustrate the electrical connectivity of several SO-DIMM configurations. The series termination resistors on CLK0 and CLK1 are not currently used and should be set to 0 ohms.
  • Page 226 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 3. 512K/1M x 64 SGRAM SO-DIMM Block Diagram (2 banks of two 256K/512K x 32) C S 1 C S 0 D Q M 0 D Q M 4 DQ[7:0] DQ[39:32] D Q M 1 D Q M 5 DQ[15:8] DQ[47:40]...
  • Page 227 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 4. 256K/512K x 32 SGRAM SO-DIMM Block Diagram (1 bank of one 256K/512K x 32) C S 0 D Q M 0 DQ[7:0] D Q M 1 DQ[15:8] 5 1 2 K x 3 2 D Q M 2 2 5 6 K x 3 2 DQ[23:16]...
  • Page 228 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 5. 512K/1M x 32 SGRAM SO-DIMM Block Diagram (2 banks of one 256K/512K x 32) C S 1 C S 0 D Q M 0 DQ[7:0] D Q M 1 DQ[15:8] 5 1 2 K x 3 2 5 1 2 K x 3 2 D Q M 2 2 5 6 K x 3 2...

  • Page 229: Address Translation

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Address Translation Table 3 should be followed for 256Kx32 and 512Kx32 SGRAM devices. This table specifies the SGRAM device to SO-DIMM connector connections for a 256Kx32 and 512Kx32 devices. Table 3. Address Translation SODIMM 256Kx32 512Kx32 Pin #...
  • Page 230 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Table 4. Module Baseline Component Requirements Parameter Min. Max. Unit Notes Clock Period 15.0 Clock High Time Rated @ 1.4V Clock Low Time DQM#/CS# Input Setup Time Other Input Setup Time DQM#/CS# Input Hold Time Other Input Hold Time Output Valid from Clock 11.0...

  • Page 231: Resistor Strapping Options

    Vcc. Resistors should be a 4.7 Kohm resistor on the DQ lines. Serial Presence Detect EEPROM This EEPROM is optional on the module. For additional information, refer to the Intel document 66 MHz Unbuffered SDRAM SO-DIMM Specification. Revision 0.91...

  • Page 232: Electrical Characteristics

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Electrical Characteristics The module electrical characteristics are carefully controlled to allow system configurations with two separate memory arrays. This allows one module to be present, plus memory soldered directly to the motherboard or add-in card PCB. Currently, two modules are not being supported. Routing on the main board will generally be done as a T-topology.

  • Page 233: 10 Ns Timing

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics 10 nS Timing Parameter Symbol Min. Max. Unit Clock Cycle Time Tcyc 10.0 Early/Late Clock Tcsk Output Valid from Clock Output Hold from Clock Input Setup Time Input Hold Time Motherboard Clock Flight Time Tcfm Motherboard Addr/Data/Cntrl Flight Time Txfm...

  • Page 234: Timing Diagrams

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics A.C Timing Diagrams Figure 6. Address/Control A.C. Timing Parameters tcyc tcsk CLK to Memory CLK to Gfx Ctrl Addr/Ctrl Addr/Ctrl Output txfm Addr/Ctrl at S O - D I M M Interface txfs Addr/Ctrl Input A005.vsd Figure 7.
  • Page 235 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 8. Data Read A.C. Timing Paramters tcyc tcsk CLK to Memory CLK to Gfx Ctrl Data Data Output txfm Data at SO-DIMM Interface txfs Data Input A007.vsd Revision 0.91...

  • Page 236: Pcb Layout Considerations

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics PCB Layout Considerations To insure proper signal integrity, the module routing must be taken under careful considerations. This section outlines PCB layout considerations for the SO-DIMM module. Each section looks at three separate topologies; one for clocks, one for control/address, and one for data.

  • Page 237: Clock Routing And Chip Selects

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Clock Routing and Chip Selects Clock and chip select loading is two loads per line, maximum. Routing should be performed using a T-topology, as shown below: Figure 9. T-Topology Clock Routing A008.vsd The following table lists the allowable stub lengths for the clock and chip select routing. Table 6.

  • Page 238: Address/Control Routing

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Address/Control Routing The following table lists the allowable stub lengths for the address/control routing. Figure 10.Address and Control Routing B a n k 1 B a n k 0 10 ohm A009.vsd Table 7. Stub Lengths (Address/Control Routing) SDRAM/SGRAM Clock Frequency Parameters...

  • Page 239: Data Routing

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Data Routing Data lodading is two loads per line, maximum. Routing should be performed using a T-topology, as shown below. Figure 11.Data Routing Bank 1 Bank 0 A010.vsd Byte-ordering (along with the respective Data Mask, DQM) within the SDRAM/SGRAM should be swapped to optimize routing.
  • Page 240 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Table 9. Stub Lengths (Data Line Routing) SDRAM/SGRAM Clock Frequency Parameters 15 nS 12 nS 10 nS 8 nS Units Min. Min. Min. Min. n+75 n+75 n+75 n+75 total length n+150 n+150 n+150 n+150 Stub d is used for the strapping resistors on DQ29-DQ31, and is optional.

  • Page 241: Electrical Specifications

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Electrical Specifications The following information is from the Intel PC SDRAM Specification, version 1.1, April 1996. It is provided here for convenience SDRAM/SGRAM Component Absolute Maximum D.C. Ratings Table 10. Absolute Maximum Ratings Symbol Parameter Min.

  • Page 242: Memory Timing

    SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Memory Timing Individual DRAM component devices are required to follow the AC timings specified in the Intel “PC SGRAM” specification. Devices which can not meet the minimum timing set forth. must program a lower clock speed.
  • Page 243 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Appendix A PCB Layout This section show an example of a PQFP/TQFP SO-DIMM module routed as a six-layer PCB. Figure 12.Silk Screen - Primary Side Figure 13.Silk Screen - Secondary Side Revision 0.91...
  • Page 244 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 14.Primary Side (layer 1) Figure 15.VCC Plane (layer 2) Revision 0.91...
  • Page 245 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 16.Inner-Signal (layer 3) Figure 17.Inner-Signal (layer 4) Revision 0.91...
  • Page 246 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics Figure 18.Ground Plane (layer 5) Figure 19.Secondary Side (layer 6) Revision 0.91...

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