Pin Configuration - Philips LC4.31E Service Manual

EN 146 9. LC4.31E AA
9.5.3 Diagram B7+B8+B9, Type GM1501 (IC7801, Genesis)
Block Diagram
14.318 M H z
Cr y s tal
Reference
D V I-C o mp lian t
I nput
DDC2Bi
DVI
A n al og RGB
I nput
DDC2Bi
analog
8/16 /24 b i t
v i deo
( 4 :4 :4 / 4 :2 :2 /
CCIR656)
8/ 16 bi t v i deo
4: 2: 2/CCIR656

Pin Configuration

A
NC
B
B L U E -
C
G R E E N -
D
R E D -
E
ADC_AGND ADC_AGND ADC_3.3 ADC_AGND
F
NC
VDDA33_
G
FPLL
VDDD33_
H
SDDS
VDDD33_
J
DDDS
K
RESETn
L
O C M _ I N T 2 O C M _ I N T 1
M
O C M _ U D O O C M _ U D I
N
V G A _ S D A V G A _ S C L
P
O C M _ C S 1 n O C M _ C S 2 n MSTR_SDA MSTR_SCL
R
R O M _ C S n O C M _ R E n OCM_ W E n
OCMADDR
T
17
OCMADDR
U
13
OCMADDR
V
9
OCMADDR
W
6
OCMADDR
Y
3
AA OCMADDR
0
AB
OC M D AT A1 3 O C M D AT A1 4 OC M D AT A1 5
AC
OC M D AT A1 0 O C M D AT A1 1 OC M D AT A1 2
AD O C M D A T A 9 O C M D A T A 6 O C M D A T A 3 O C M D A T A 0
AE O C M D A T A 8 O C M D A T A 5 OCMDATA2
AF O C M D A T A 7 O C M D A T A 4 OCMDATA1
1
Circuit Descriptions, Abbreviation List, and IC Data Sheets
2- w i re
Serial I/F JT A G GP IO
Interfa ce X186
Mi c r o -
co n t ro lle r
Int e rnal
Clock
RA M
Gener a ti on
Ul tr a-Rel i abl e
DVI Rx
Image
Captur e
and
M easu re
T r ip le A D C
ment
and PLL
Test Patte rn
Gen e rato r
Image
Captur e Vi deo
and Shrink
M easu re F ilte r
ment
ADC_3.3 ADC_1.8 ADC_1.8
A DC_ DGND
B L U E + ADC_3.3 DVI _ GND
A DC_ DGND
G R E E N + S O G ADC_AGND NC
R E D + ADC_3.3 ADC_AGND NC
VDDD33_ VSSA33_ VDDA33_
PLL RPLL RPLL
VSSD33_
T C L K X T A L
PLL
VSSA33_ VDDA33_ VSSA33_
SDDS SDDS FPLL
VSSA33_ VDDA33_ VSSD33_
DDDS DDDS SDDS
ACS_ VSSD33_
NC
RSET_HD DDDS
AVSY NC AHSY NC
I R 0 I R 1
D V I _ S D A D V I _ S C L
EX T C L K
OCMADDR OCMADDR
OCM_CS0n
18 19
OCMADDR OCMADDR OCMADDR
14 15 16
OCMADDR OCMADDR OCMADDR
10 11 12
OCMADDR OCMADDR
IO_3 .3
7 8
OCMADDR OCMADDR
IO_3 .3
4 5
OCMADDR OCMADDR
IO_3 .3
1 2
IO_3 .3
G P IO _ G 09_ B2
IO_3 .3
( DE GRN0 )
G P IO _ G 09_ B3 G P IO _ G 08_ B0
( DE GRN1 )
G P IO _ G 09_ B0 G P IO _ G 09_ B4 G P IO _ G 08_ B1
DE RE D0 D EBLU 0
( ) ( )
G P IO _ G 09_ B1 G P IO _ G 09_ B5 G P IO _ G 08_ B2
DE RE D1 D EBLU 1
( ) ( )
2 3 4 5
Figure 9-5 Internal block diagram and pin configuration
Para lle l
ROM
IF /exte r n a l
mic r o
In fra- red R x Lo w
Externa l
B a n d w i d t h
ROM I/ F
A D C
In tern a l
ROM
Gr aphi cs Gr aphi cs
Shrink Zoom
F ilte r F ilte r
OSD
Frame
C o n t ro lle r
Store
Contr o l
Color Table
RA M s
M o ti on
Ad a p t .
Vi deo
Zoom
3: 2/2: 2
F ilte r
detecti on
DDR SDR A M
I/F
RX C+ DVI _ GND RX 0 + R X 1 +
RX C- DVI _ GND RX 0 - R X 1 -
DVI_3.3 DVI _ GND DVI_3.3 DVI_3.3
DVI_1.8 DVI _ GND DVI_1.8 DVI_1.8
CORE_1.8 CORE_1. 8
CORE_1.8 CORE_1. 8
G P IO _ G 07_ B2
IO_3 .3 DCLK IO_3 .3
( DE RE D4 )
G P IO _ G 08_ B5 G P IO _ G 07_ B3
G P IO _ G 07_ B6
DEN
( DORE D0 ) ( DOB L U1 ) ( DE RE D5 )
G P IO _ G 08_ B3 G P IO _ G 07_ B0 G P IO _ G 07_ B4 G P IO _ G 07_ B7
DORE D1 DOGRN1 DE RE D2 DE RE D6
( ) ( ) ( ) ( )
G P IO _ G 08_ B4 G P IO _ G 07_ B1 G P IO _ G 07_ B5
DOGRN0 DOB L U0 DE RE D3 DE RE D7
( ) ( ) ( ) ( )
6 7 8 9
Pul se W i dth
M odul ator
TTL/
Panel Data
LVDS
/C o n t ro l
Tx
Di spl a y
Ti mi ng
Gen e rato r
TM
RealColor
Output
Bl ender
R X 2 + DVI _ GND LBADC_I N 3 D_GND
R X 2 - REX T LBADC_I N 2 D_GND
DVI_3.3 DVI_3.3 LBADC_I N 1 LBADC_33
LBADC_
DVI_1.8 DVI _ GND L B A DC_ GND
RETURN
D_GND D_GND
D_GND CORE_1. 8 D_GND D_GND
D_GND D_GND D_GND D_GND
D_GND D_GND D_GND D_GND
D_GND D_GND D_GND D_GND
D_GND D_GND D_GND D_GND
D_GND CORE_1. 8 D_GND D_GND
D_GND D_GND
SHIELD[1 ]
IO_3 .3 LVDSB_3.3
LVD SB_ GN D
(DE G RN3 )
SHIELD[2 ]
LVDSB_3.3 LVDSB_3.3
( DE RE D8 ) (DE G RN4 )
SHIELD[3 ] BC + SHIELD[4 ]
( DE RE D9 ) (DE G RN5 ) (DE G RN8 ) (DE B L U2 )
SHIELD[0 ] B3+ B3- BC -
(DE G RN2 ) (DE G RN6 ) (DE G RN7 ) (DE G RN9 )
1 0 11 12 1 3
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