Signalling Circuit; Encode; Decode; High-Speed Data (Dtmf) - Kenwood TK-380 Service Manual

TK-380

7. Signalling Circuit

7-1. Encode

Low-speed data (QT,DQT)
Low-speed data is output from pin 1 of the CPU. The signal
passes through a low-pass CR filter, and goes to the summing
amplifier (IC7 1/2). The signal is mixed with the audio signal
and goes to the VCO (A1) and VCXO (X1) modulation input
after passing through the D/A converter (IC8) for BAL
adjustment.
High-speed data (5 tone, DTMF)
High-speed data is output from pin 2 of the CPU. The signal
passes through a low-pass filter consisting of IC10, and
provides a TX HSD tone and a RX HSD tone TX HSD deviation
making an adjustment by microprocessor is passed through
the D/A convertor (IC8), and then applied to the audio processor
(IC13).
The signal is mixed with the audio signal and goes to the
VCO and VCXO, the RX HSD tone is passed a summing
amplifier (IC7 2/2), the D/A converter (IC8) for audio control,
audio power amplifier and then to the speaker.
FFSK
ESN utilizes 1200bps FFSK signal. FFSK signal is output
from pin 6 of IC13. The signal passes through the D/A converter
(IC8) for the FFSK deviation adjustment. and is routed to the
VCO. When encoding FFSK, the microphone input signal is
muted.
IC19
CPU
IC10
2
HSD
LPF
OUT
LSD
OUT
1
R162
R166
Fig. 13 Encode
24
CIRCUIT DESCRIPTION
RX Audio
I6
O6
AF
SUM
AMP
IC7 (2/2)
IC8
D/A (ADJ)
I3 O3
SUM
I5
O5 MIC IN
I2
O2
SUM
IC7(1/2)
IC1
O1 BUFF
AMP

7-2. Decode

Low-speed data (QT,DQT)
The demodulated signal from the IF IC (IC12) is amplified
by IC4 (2/2) and passes through a low-pass filter (IC11) to
remove audio components. The signal is input to pin 95 of the
CPU.
The CPU digitizes this signal, performs processing such as
DC restoration, and decodes the signal.

High-speed data (DTMF)

The DTMF input signal from the IF IC (IC12) is amplified by
IC4 (2/2) and goes to IC16, the DTMF decoder. The decoded
information is then processed by the CPU. During transmission
and standby, the DTMF IC is set to the power down mode
when the PD terminal is High. When the line is busy, the PD
terminal becomes Low, the power down mode is canceled and
decoding is carried out.
High-speed data (2 tone, 5 tone)
The demodulated signal from the IF IC (IC12) is amplified
by IC4 (2/2) and passes through an audio processor (IC13)
and band-pass filter (IC2) to remove a low-speed data. The
CPU digitizes this signal, performs processing such as DC
restoration, and decodes the signal.
FFSK
The FFSK input signal from the IF IC is amplified by IC4
(1/ 2) and goes to pin 5 of IC13. The signal is demodulated by
FFSK demodulator in IC13. The demodulated data goes to
the CPU for processing.
IC13
IC4
AMP
A1
MD
VCO
X1
MB
VCXO
IC13
XOUT
IC13 IC2
AF IC BPF
23
IC11
LSD
LPF IN
IC16
DCK,SD,STD
DTMF
DECODE
OSC1
PD
11
Fig. 14 Decode
3
HSD
IN
IC19
CPU
IC22