LG 47LA790V Service Manual page 26

IC100
LG1154D_H13D
F15
M0_DDR_A[0] M0_DDR_A0
F13
M0_DDR_A[1] M0_DDR_A1
F17
M0_DDR_A[2] M0_DDR_A2
F19
M0_DDR_A3
M0_DDR_A[3]
E10
M0_DDR_A4
M0_DDR_A[4]
E18
M0_DDR_A5
M0_DDR_A[5]
E11
M0_DDR_A[6] M0_DDR_A6
F18
M0_DDR_A[7] M0_DDR_A7
F11
M0_DDR_A[8] M0_DDR_A8
F16
M0_DDR_A[9] M0_DDR_A9
E9 VDDC15_M0
M0_DDR_A[10] M0_DDR_A10
E12
M0_DDR_A[11] M0_DDR_A11
E13
M0_DDR_A[12] M0_DDR_A12 R520
E16
M0_DDR_A[13] M0_DDR_A13 10K
F12
M0_DDR_A[14] M0_DDR_A14
F14
M0_DDR_A15
M0_DDR_A[15]
E19
M0_DDR_BA[0] M0_DDR_BA0
F10
M0_DDR_BA[1] M0_DDR_BA1
E15
M0_DDR_BA[2] M0_DDR_BA2
B10
M0_DDR_U_CLK M0_U_CLK
A10
M0_DDR_U_CLKN M0_U_CLKN
A19
M0_DDR_D_CLK M0_D_CLK
B19
M0_DDR_D_CLKN M0_D_CLKN
E14
M0_DDR_CKE M0_DDR_CKE
F21
M0_DDR_ODT
M0_DDR_ODT
E21
M0_DDR_RASN M0_DDR_RASN
E20
M0_DDR_CASN M0_DDR_CASN
F20
M0_DDR_WEN M0_DDR_WEN
E17
VDDC15_M0
M0_DDR_RESET_N M0_DDR_RESET_N
F9 240 R500
M0_DDR_ZQCAL
1%
B20
M0_DDR_DQS[0] M0_DDR_DQS0
A20
M0_DDR_DQS_N0
M0_DDR_DQS_N[0]
C19
M0_DDR_DQS1
M0_DDR_DQS[1]
D19
M0_DDR_DQS_N[1] M0_DDR_DQS_N1
A11
M0_DDR_DQS[2] M0_DDR_DQS2
B11
M0_DDR_DQS_N[2] M0_DDR_DQS_N2
C10
M0_DDR_DQS[3] M0_DDR_DQS3
D10
M0_DDR_DQS_N[3] M0_DDR_DQS_N3
D18
M0_DDR_DM[0] M0_DDR_DM0
C20
M0_DDR_DM[1] M0_DDR_DM1
D9
M0_DDR_DM[2] M0_DDR_DM2
C11
M0_DDR_DM3
M0_DDR_DM[3]
D22
M0_DDR_DQ0
M0_DDR_DQ[0]
C15
M0_DDR_DQ1
M0_DDR_DQ[1]
C23
VDDC15_M0
M0_DDR_DQ[2] M0_DDR_DQ2
D16
M0_DDR_DQ[3] M0_DDR_DQ3
B24
M0_DDR_DQ[4] M0_DDR_DQ4
B15
M0_DDR_DQ[5] M0_DDR_DQ5
D23
M0_DDR_DQ[6] M0_DDR_DQ6
A15
M0_DDR_DQ[7] M0_DDR_DQ7
C16
M0_DDR_DQ[8] M0_DDR_DQ8
D21
M0_DDR_DQ9
M0_DDR_DQ[9]
D17
M0_DDR_DQ10
M0_DDR_DQ[10]
C22
M0_DDR_DQ11
M0_DDR_DQ[11]
C18
M0_DDR_DQ12
M0_DDR_DQ[12]
C21
M0_DDR_DQ[13] M0_DDR_DQ13
C17
M0_DDR_DQ[14] M0_DDR_DQ14
D20
M0_DDR_DQ[15] M0_DDR_DQ15
C13
M0_DDR_DQ[16] M0_DDR_DQ16
D7
M0_DDR_DQ[17] M0_DDR_DQ17
D13
M0_DDR_DQ[18] M0_DDR_DQ18
C6
M0_DDR_DQ[19] M0_DDR_DQ19
D14
M0_DDR_DQ20
M0_DDR_DQ[20]
D6
M0_DDR_DQ21
M0_DDR_DQ[21]
C14
M0_DDR_DQ22
M0_DDR_DQ[22]
A5
M0_DDR_DQ23
M0_DDR_DQ[23]
C7
M0_DDR_DQ24
M0_DDR_DQ[24]
D12
M0_DDR_DQ[25] M0_DDR_DQ25
D8
M0_DDR_DQ[26] M0_DDR_DQ26
B13
M0_DDR_DQ[27] M0_DDR_DQ27
C9
M0_DDR_DQ[28] M0_DDR_DQ28
C12
M0_DDR_DQ[29] M0_DDR_DQ29
C8
M0_DDR_DQ[30] M0_DDR_DQ30
D11
M0_DDR_DQ31
M0_DDR_DQ[31]
IC100
LG1154D_H13D
N6
M1_DDR_A0
M1_DDR_A[0]
R6
M1_DDR_A[1] M1_DDR_A1
L6
M1_DDR_A[2] M1_DDR_A2
J6
M1_DDR_A[3] M1_DDR_A3
U5
M1_DDR_A[4] M1_DDR_A4 VDDC15_M1
J5
M1_DDR_A[5] M1_DDR_A5
T5
M1_DDR_A[6] M1_DDR_A6
K6
M1_DDR_A[7] M1_DDR_A7
U6 R521
M1_DDR_A[8] M1_DDR_A8
M6 10K
M1_DDR_A9
M1_DDR_A[9]
V5
M1_DDR_A10
M1_DDR_A[10]
R5 M1_DDR_RESET_N
M1_DDR_A11
M1_DDR_A[11]
P5
M1_DDR_A[12] M1_DDR_A12
L5
M1_DDR_A[13] M1_DDR_A13
T6
M1_DDR_A[14] M1_DDR_A14 M1_D_CLK
P6
M1_DDR_A[15] M1_DDR_A15
H5
M1_DDR_BA[0] M1_DDR_BA0
V6
M1_DDR_BA[1] M1_DDR_BA1
M5 M1_D_CLKN
M1_DDR_BA[2] M1_DDR_BA2
R2
M1_U_CLK
M1_DDR_U_CLK
R1
M1_U_CLKN
M1_DDR_U_CLKN
F1
M1_DDR_D_CLK M1_D_CLK
F2
M1_DDR_D_CLKN M1_D_CLKN VDDC15_M1
N5
M1_DDR_CKE M1_DDR_CKE
G6 M1_DDR_VREFCA
M1_DDR_ODT M1_DDR_ODT
F5
M1_DDR_RASN M1_DDR_RASN
G5
M1_DDR_CASN M1_DDR_CASN
H6
M1_DDR_WEN M1_DDR_WEN
K5
M1_DDR_RESET_N
M1_DDR_RESET_N
F6 240 R501
M1_DDR_ZQCAL
1%
E2
M1_DDR_DQS[0] M1_DDR_DQS0
E1
M1_DDR_DQS_N[0] M1_DDR_DQS_N0
F3
M1_DDR_DQS[1] M1_DDR_DQS1
F4
M1_DDR_DQS_N[1] M1_DDR_DQS_N1
P1
M1_DDR_DQS[2] M1_DDR_DQS2
P2
M1_DDR_DQS_N[2] M1_DDR_DQS_N2
R3
M1_DDR_DQS[3] M1_DDR_DQS3
R4
M1_DDR_DQS_N3
M1_DDR_DQS_N[3]
VDDC15_M1
G4
M1_DDR_DM[0] M1_DDR_DM0
E3
M1_DDR_DM[1] M1_DDR_DM1 M1_DDR_VREFDQ
T4
M1_DDR_DM[2] M1_DDR_DM2
P3
M1_DDR_DM[3] M1_DDR_DM3
C4
M1_DDR_DQ[0] M1_DDR_DQ0
K3
M1_DDR_DQ[1] M1_DDR_DQ1
B3
M1_DDR_DQ[2] M1_DDR_DQ2
J4
M1_DDR_DQ[3] M1_DDR_DQ3
A3
M1_DDR_DQ4
M1_DDR_DQ[4]
K2
M1_DDR_DQ5
M1_DDR_DQ[5]
B4
M1_DDR_DQ6
M1_DDR_DQ[6]
K1
M1_DDR_DQ7
M1_DDR_DQ[7]
J3
M1_DDR_DQ[8] M1_DDR_DQ8
D4
M1_DDR_DQ[9] M1_DDR_DQ9
H4
M1_DDR_DQ[10] M1_DDR_DQ10
C3
M1_DDR_DQ[11] M1_DDR_DQ11
G3
M1_DDR_DQ[12] M1_DDR_DQ12
D3
M1_DDR_DQ[13] M1_DDR_DQ13
H3
M1_DDR_DQ[14] M1_DDR_DQ14
E4
M1_DDR_DQ15
M1_DDR_DQ[15]
M3
M1_DDR_DQ16
M1_DDR_DQ[16]
V4
M1_DDR_DQ17
M1_DDR_DQ[17]
M4
M1_DDR_DQ18
M1_DDR_DQ[18]
W3
M1_DDR_DQ[19] M1_DDR_DQ19
L4
M1_DDR_DQ[20] M1_DDR_DQ20
W4
M1_DDR_DQ[21] M1_DDR_DQ21
L3
M1_DDR_DQ[22] M1_DDR_DQ22
Y2
M1_DDR_DQ[23] M1_DDR_DQ23
V3
M1_DDR_DQ[24] M1_DDR_DQ24
N4
M1_DDR_DQ[25] M1_DDR_DQ25
U4
M1_DDR_DQ26
M1_DDR_DQ[26]
M2
M1_DDR_DQ27
M1_DDR_DQ[27]
T3
M1_DDR_DQ28
M1_DDR_DQ[28]
N3
M1_DDR_DQ29
M1_DDR_DQ[29]
U3
M1_DDR_DQ[30] M1_DDR_DQ30
P4
M1_DDR_DQ[31] M1_DDR_DQ31
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
M0_DDR_CKE
R541
10K M0_DDR_A0
M0_DDR_A1
M0_DDR_RESET_N M0_DDR_A2
M0_DDR_A3
M0_DDR_A4
M0_DDR_A5
M0_D_CLK M0_U_CLK M0_DDR_A6
M0_DDR_A7
M0_DDR_A8
M0_DDR_A9
M0_DDR_A10
M0_D_CLKN M0_U_CLKN
M0_DDR_A11
M0_DDR_A12
M0_DDR_A13
M0_DDR_A14
M0_DDR_A15
M0_DDR_BA0
M0_DDR_BA1
VDDC15_M0 M0_DDR_BA2
M0_1_DDR_VREFCA M0_D_CLK
M0_DDR_VREFCA
M0_D_CLKN
M0_DDR_CKE
M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_WEN
M0_DDR_RESET_N
M0_DDR_DQS0
M0_DDR_DQS_N0
M0_DDR_DQS1
M0_DDR_DQS_N1
VDDC15_M0
M0_DDR_DM0
M0_1_DDR_VREFDQ
M0_DDR_DM1
M0_DDR_VREFDQ
M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ8
M0_DDR_DQ9
M0_DDR_DQ10
M0_DDR_DQ11
M0_DDR_DQ12
M0_DDR_DQ13
M0_DDR_DQ14
M0_DDR_DQ15
M1_DDR_CKE
M1_DDR_A0
M1_DDR_A1
R540 M1_DDR_A2
10K M1_DDR_A3
M1_DDR_A4
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8
M1_DDR_A9
M1_U_CLK
M1_DDR_A10
M1_DDR_A11
M1_DDR_A12
M1_DDR_A13
M1_U_CLKN
M1_DDR_A14
M1_DDR_A15
M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2
VDDC15_M1
M1_D_CLK
M1_1_DDR_VREFCA
M1_D_CLKN
M1_DDR_CKE
M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_RESET_N
M1_DDR_DQS0
M1_DDR_DQS_N0
M1_DDR_DQS1
M1_DDR_DQS_N1
VDDC15_M1
M1_DDR_DM0
M1_DDR_DM1
M1_1_DDR_VREFDQ
M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
DDR_SAMSUNG
DDR_HYNIX
IC500-*1
IC500 H5TQ4G63AFR-PBC
M0_DDR_VREFCA
K4B4G1646B-HCK0 N3 M8
P7 A0 VREFCA
P3 A1 A2
N2 A3 VREFDQ H1
P8 A4
P2 A5
DDR3 R8 A6 ZQ L8
T8 R2 A7
R3 A8 B2
4Gbit M0_DDR_VREFDQ L7 A9 VDD_1 D9
N3 M8 R7 A10/AP VDD_2 G7
N7 A11 VDD_3 K2
A0 VREFCA T3 A12/BC VDD_4 K8
P7 (x16) T7 A13 VDD_5 N1
M7 A14 VDD_6 N9
A1 A15 VDD_7 VDD_8 R1
P3 M2 BA0 VDD_9 R9
N8 BA1
A2 M3 BA2
N2 H1 VDDQ_1 A1
J7 K7 CK VDDQ_2 C1 A8
A3 VREFDQ K9 CK VDDQ_3 C9
P8 CKE VDDQ_4 D2
L2 VDDQ_5 E9
A4 K1 CS VDDQ_6 F1
P2 VDDC15_M0 J3 ODT VDDQ_7 H2
K3 RAS VDDQ_8 H9
A5 R542 L3 WE CAS VDDQ_9
R8 L8 NC_1 J1
T2 RESET NC_2 J9
A6 ZQ NC_3 L1
R2 NC_4 L9
240 F3 DQSL
A7 G3 DQSL
1% C7 A9
T8 B7 DQSU VSS_1 B3
A8 DQSU VSS_2 E1
E7 VSS_3 G8
R3 B2 D3 DML VSS_4 J2
A9 VDD_1 DMU VSS_5 J8
E3 DQL0 VSS_7 VSS_6 M1
L7 D9 F7 DQL1 VSS_8 M9
F2 DQL2 VSS_9 P1
A10/AP VDD_2 F8 DQL3 VSS_10 P9
R7 G7 H3 DQL4 VSS_11 T1
H8 DQL5 VSS_12 T9
A11 VDD_3 G2 H7 DQL6
N7 K2 DQL7 B1
D7 VSSQ_1 B9
A12/BC VDD_4 C3 DQU0 VSSQ_2 D1
T3 K8 C8 DQU1 VSSQ_3 D8
C2 DQU2 VSSQ_4 E2
A13 VDD_5 A7 DQU3 VSSQ_5 E8
T7 N1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9
B8 DQU6 VSSQ_8 G1
A14 VDD_6 A3 DQU7 VSSQ_9 G9
M7 N9
A15 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2 0.1uF
C534
RAS VDDQ_8
K3 H9 0.1uF
C535
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3
DQSL
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2
VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
DDR_SAMSUNG
IC501
M1_DDR_VREFCA DDR_HYNIX
K4B4G1646B-HCK0
IC501-*1
H5TQ4G63AFR-PBC
N3 M8
P7 A0 VREFCA
P3 A1
M1_DDR_VREFDQ N2 A2 H1
P8 A3 VREFDQ
N3 DDR3 M8 P2 A4
R8 A5 L8
A0 VREFCA R2 A7 A6 ZQ
P7 4Gbit T8 A8
R3 A9 VDD_1 B2
A1 L7 A10/AP VDD_2 D9
P3 R7 A11 VDD_3 G7
(x16) N7 A12/BC VDD_4 K2
A2 T3 T7 A13 VDD_5 K8 N1
N2 H1 M7 A14 VDD_6 N9
A15 VDD_7 R1
A3 VREFDQ M2 VDD_8 R9
P8 N8 BA0 VDD_9
M3 BA1
A4 BA2 A1
P2 J7 CK VDDQ_2 VDDQ_1 A8
K7 CK VDDQ_3 C1
A5 K9 CKE VDDQ_4 C9
R8 L8 VDDQ_5 D2
R543 240 L2 CS VDDQ_6 E9
A6 ZQ K1 J3 ODT VDDQ_7 H2 F1
R2 K3 RAS VDDQ_8 H9
VDDC15_M1 L3 CAS VDDQ_9
A7 WE J1
T2 NC_1 J9
T8 RESET NC_2 L1
A8 NC_3 L9
F3 NC_4
R3 B2 G3 DQSL DQSL
A9 VDD_1
C7 DQSU VSS_1 A9
L7 D9 B7 DQSU VSS_2 B3
VSS_3 E1
A10/AP VDD_2 D3 E7 DML VSS_4 G8 J2
R7 G7 DMU VSS_5 J8
E3 VSS_6 M1
A11 VDD_3 F7 DQL0 VSS_7 M9
N7 K2 F2 DQL1 VSS_8 P1
F8 DQL2 VSS_9 P9
A12/BC VDD_4 H3 DQL3 VSS_10 T1
T3 K8 H8 DQL5 DQL4 VSS_12 VSS_11 T9
G2 DQL6
A13 VDD_5 H7 DQL7
T7 N1 VSSQ_1 B1
D7 DQU0 VSSQ_2 B9
A14 VDD_6 C3 DQU1 VSSQ_3 D1
M7 N9 C2 C8 DQU2 VSSQ_4 E2 D8
A7 DQU3 VSSQ_5 E8
A15 VDD_7 A2 DQU4 VSSQ_6 F9
R1 B8 DQU5 VSSQ_7 G1
A3 DQU6 VSSQ_8 G9
VDD_8 DQU7 VSSQ_9
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK
VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
C529 0.1uF
RAS VDDQ_8
K3 H9
C530 0.1uF
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3
DQSL
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
DDR_SAMSUNG
IC502
M0_1_DDR_VREFCA DDR_HYNIX
IC502-*1
K4B4G1646B-HCK0
H5TQ4G63AFR-PBC
N3 A0 VREFCA M8
P7 A1
M0_1_DDR_VREFDQ P3 A2
DDR3 N2 A3 VREFDQ H1
P8 A4
P2 R8 A5 L8
N3 M8 R2 A6 ZQ
4Gbit T8 A7
M0_DDR_A0 A0 VREFCA R3 A8 B2
P7 L7 A9 VDD_1 D9
(x16) R7 A10/AP VDD_2 G7
M0_DDR_A1 A1 N7 A11 VDD_3 K2
P3 T3 A13 A12/BC VDD_5 VDD_4 K8
T7 A14 VDD_6 N1
M0_DDR_A2 A2 M7 A15 VDD_7 N9
N2 H1 VDD_8 R1
M2 BA0 VDD_9 R9
M0_DDR_A3 A3 VREFDQ M3 N8 BA1
BA2 A1
P8 J7 VDDQ_1 A8
M0_DDR_A4 A4 K7 CK VDDQ_2 C1
K9 CK VDDQ_3 C9
P2 VDDC15_M0 CKE VDDQ_4 D2
M0_DDR_A5 A5 L2 VDDQ_5 E9
R544 K1 CS VDDQ_6 F1
R8 L8 J3 ODT RAS VDDQ_7 VDDQ_8 H2
M0_DDR_A6 A6 ZQ K3 CAS VDDQ_9 H9
L3 WE
R2 240 NC_1 J1
M0_DDR_A7 T2 RESET NC_2 J9
A7 1% NC_3 L9 L1
T8 F3 NC_4
M0_DDR_A8 G3 DQSL
A8 DQSL
R3 B2 C7 A9
B7 DQSU VSS_1 B3
M0_DDR_A9 A9 VDD_1 DQSU VSS_2 E1
L7 D9 E7 DML VSS_4 VSS_3 G8
D3 DMU VSS_5 J2
M0_DDR_A10 A10/AP VDD_2 VSS_6 J8
R7 G7 E3 DQL0 VSS_7 M1
F7 DQL1 VSS_8 M9
M0_DDR_A11 A11 VDD_3 F2 DQL2 VSS_9 P1
N7 K2 H3 F8 DQL3 VSS_10 P9 T1
H8 DQL4 VSS_11 T9
M0_DDR_A12 A12/BC VDD_4 G2 DQL5 VSS_12
T3 K8 H7 DQL6
DQL7 B1
M0_DDR_A13 A13 VDD_5 D7 VSSQ_1 B9
T7 N1 C3 DQU0 VSSQ_2 D1
C8 DQU1 DQU2 VSSQ_4 VSSQ_3 D8
M0_DDR_A14 A14 VDD_6 C2 DQU3 VSSQ_5 E2
A7 DQU4 VSSQ_6 E8
M7 N9 A2 DQU5 VSSQ_7 F9
M0_DDR_A15 A15 VDD_7 B8 DQU6 VSSQ_8 G1
A3 DQU7 VSSQ_9 G9
R1
VDD_8
M2 R9
M0_DDR_BA0 BA0 VDD_9
N8
M0_DDR_BA1
BA1
M3
M0_DDR_BA2
BA2
A1
VDDQ_1
J7 A8
M0_U_CLK CK VDDQ_2
K7 C1
M0_U_CLKN CK VDDQ_3
K9 C9
M0_DDR_CKE CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
M0_DDR_ODT ODT VDDQ_7
J3 H2 C566 0.1uF
M0_DDR_RASN RAS VDDQ_8
K3 H9 C567 0.1uF
M0_DDR_CASN CAS VDDQ_9
L3
M0_DDR_WEN
WE
J1
NC_1
T2 J9
M0_DDR_RESET_N RESET NC_2
L1
NC_3
L9
NC_4
F3
M0_DDR_DQS2 DQSL
G3
M0_DDR_DQS_N2 DQSL
C7 A9
M0_DDR_DQS3 DQSU VSS_1
B7 B3
M0_DDR_DQS_N3 DQSU VSS_2
E1
VSS_3
E7 G8
M0_DDR_DM2
DML VSS_4
D3 J2
M0_DDR_DM3
DMU VSS_5
J8
VSS_6
E3 M1
M0_DDR_DQ16 DQL0 VSS_7
F7 M9
M0_DDR_DQ17 DQL1 VSS_8
F2 P1
M0_DDR_DQ18 DQL2 VSS_9
F8 P9
M0_DDR_DQ19 DQL3 VSS_10
H3 T1
M0_DDR_DQ20 DQL4 VSS_11
H8
T9
M0_DDR_DQ21 DQL5 VSS_12
G2
M0_DDR_DQ22 DQL6
H7
M0_DDR_DQ23 DQL7
B1
VSSQ_1
D7 B9
M0_DDR_DQ24
DQU0 VSSQ_2
C3 D1
M0_DDR_DQ25
DQU1 VSSQ_3
C8 D8
M0_DDR_DQ26 DQU2 VSSQ_4
C2 E2
M0_DDR_DQ27 DQU3 VSSQ_5
A7 E8
M0_DDR_DQ28 DQU4 VSSQ_6
A2 F9
M0_DDR_DQ29 DQU5 VSSQ_7
B8 G1
M0_DDR_DQ30 DQU6 VSSQ_8
A3
G9
M0_DDR_DQ31 DQU7 VSSQ_9
Real USE : 1Gbit
H5TQ1G63DFR-PBC(x16)
1Gbit : T7(NC_6)
4Gbit : T7(A14) DDR_SAMSUNG
IC503 DDR_HYNIX
M1_1_DDR_VREFCA IC503-*1
K4B4G1646B-HCK0
H5TQ4G63AFR-PBC
N3 M8
P7 A0 VREFCA
P3 A1
N2 A2 H1
P8 A3 VREFDQ
DDR3 M1_1_DDR_VREFDQ P2 A4
N3 M8 R8 A5 L8
M1_DDR_A0 A0 VREFCA R2 A6 A7 ZQ
T8 A8
P7 4Gbit R3 A9 VDD_1 B2
M1_DDR_A1 A1 L7 A10/AP VDD_2 D9
R7 A11 VDD_3 G7
P3 (x16) N7 A12/BC VDD_4 K2
M1_DDR_A2 T7 T3 A13 VDD_5 K8 N1
A2 M7 A14 VDD_6 N9
N2 H1 A15 VDD_7 R1
M1_DDR_A3 M2 VDD_8 R9
A3 VREFDQ N8 BA0 VDD_9
P8 M3 BA1
BA2 A1
M1_DDR_A4 A4 J7 CK VDDQ_2 VDDQ_1 A8
P2 K7 CK VDDQ_3 C1
K9 CKE VDDQ_4 C9
M1_DDR_A5 A5 VDDQ_5 D2
R8 L8 R545 L2 CS VDDQ_6 E9
240 K1 J3 ODT VDDQ_7 H2 F1
M1_DDR_A6 A6 ZQ K3 RAS VDDQ_8 H9
R2 L3 CAS VDDQ_9
WE J1
M1_DDR_A7 A7 T2 NC_1 J9
T8 VDDC15_M1 RESET NC_2 L1
NC_3 L9
M1_DDR_A8 A8 F3 NC_4
R3 B2 G3 DQSL DQSL
M1_DDR_A9 A9 VDD_1 C7 DQSU VSS_1 A9
B7 DQSU VSS_2 B3
L7 D9 VSS_3 E1
M1_DDR_A10 A10/AP VDD_2 E7 D3 DML VSS_4 J2 G8
DMU VSS_5 J8
R7 G7 E3 VSS_6 M1
M1_DDR_A11 A11 VDD_3 F7 DQL0 VSS_7 M9
F2 DQL1 VSS_8 P1
N7 K2 F8 DQL2 VSS_9 P9
M1_DDR_A12 A12/BC VDD_4 H3 DQL3 VSS_10 T1
H8 DQL5 DQL4 VSS_12 VSS_11 T9
T3 K8 G2 DQL6
M1_DDR_A13 H7 DQL7
A13 VDD_5 VSSQ_1 B1
T7 N1 D7 DQU0 VSSQ_2 B9
M1_DDR_A14 C3 DQU1 VSSQ_3 D1
A14 VDD_6 C8 C2 DQU2 VSSQ_4 D8 E2
M7 N9 A7 DQU3 VSSQ_5 E8
M1_DDR_A15 A2 DQU4 VSSQ_6 F9
A15 VDD_7 B8 DQU5 VSSQ_7 G1
R1 A3 DQU6 VSSQ_8 G9
DQU7 VSSQ_9
VDD_8
M2 R9
M1_DDR_BA0 BA0 VDD_9
N8
M1_DDR_BA1 BA1
M3
M1_DDR_BA2 BA2
A1
VDDQ_1
J7
A8
M1_U_CLK CK VDDQ_2
K7 C1
M1_U_CLKN CK VDDQ_3
K9 C9
M1_DDR_CKE CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
M1_DDR_ODT
ODT VDDQ_7
J3 H2
C561 0.1uF
M1_DDR_RASN RAS VDDQ_8
K3 H9
C562 0.1uF
M1_DDR_CASN CAS VDDQ_9
L3
M1_DDR_WEN WE
J1
NC_1
T2 J9
M1_DDR_RESET_N RESET NC_2
L1
NC_3
L9
NC_4
F3
M1_DDR_DQS2 DQSL
G3
M1_DDR_DQS_N2
DQSL
C7 A9
M1_DDR_DQS3
DQSU VSS_1
B7 B3
M1_DDR_DQS_N3 DQSU VSS_2
E1
VSS_3
E7 G8
M1_DDR_DM2 DML VSS_4
D3 J2
M1_DDR_DM3 DMU VSS_5
J8
VSS_6
E3 M1
M1_DDR_DQ16 DQL0 VSS_7
F7 M9
M1_DDR_DQ17 DQL1 VSS_8
F2 P1
M1_DDR_DQ18 DQL2 VSS_9
F8 P9
M1_DDR_DQ19
DQL3 VSS_10
H3 T1
M1_DDR_DQ20
DQL4 VSS_11
H8 T9
M1_DDR_DQ21
DQL5 VSS_12
G2
M1_DDR_DQ22 DQL6
H7
M1_DDR_DQ23 DQL7
B1
VSSQ_1
D7 B9
M1_DDR_DQ24 DQU0 VSSQ_2
C3 D1
M1_DDR_DQ25 DQU1 VSSQ_3
C8 D8
M1_DDR_DQ26 DQU2 VSSQ_4
C2 E2
M1_DDR_DQ27 DQU3 VSSQ_5
A7 E8
M1_DDR_DQ28 DQU4 VSSQ_6
A2 F9
M1_DDR_DQ29
DQU5 VSSQ_7
B8 G1
M1_DDR_DQ30
DQU6 VSSQ_8
A3 G9
M1_DDR_DQ31
DQU7 VSSQ_9
BSD-NC4_H005-HD
2012-09-14
MAIN DDR
LGE Internal Use Only