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DPX-4010,4010/PH4
QQ
3 7 63 1515 0
MICROCOMPUTER'S TERMINAL DESCRIPTION
Pin No.
Pin Name
51
P47/KEY7
52
P50/WE
53
P51/RE
54
P52/CS
55
P53/A16
56
P54/A17
57
P60/A0
58
P61/A1
59
P62/A2
60
P63/A3
61
P64/A4
62
P65/A5
63
P66/A6
64
P67/A7
65
P70/A8
66
P71/A9
67
P72/A10
68
P73/A11
69
P74/A12
70
P75/A13
71
P76/A14
TE
L 13942296513
72
P77/A15
73
P87/LED7/D7
74
P86/LED6/D6
75
P85/LED5/D5
76
P84/LED4/D4
77
P83/LED3/D3
78
P83/LED2/D2
79
P81/LED1/D1
80
P80/LED0/D0
Level: High level (active) →H (a), Low level (active) →L (a)
Panel Microcomputer MN101C10AAK (IC900: Combination PWB Unit)
Pin No.
Pin Name
1~5
6
VREF+
7
VDD
8
OSC2
9
OSC1
10
VSS
11
XI
12
XO
www
13
MMOD
14
P00/SBO0/TXD
15
P01/SBI0/RXD
.
16
P02/SBT0
17
P03/SBO1
18
P04/SBI1
19
P05/SBT1
4
Signal Name
I/O
N–F_MUTE
O
Muting of N-F when N-F is selected [H: Muting. L: Normal]
AUDIO1
O
LINE OUT switching [H: FRONT. L: REAR]
DSP_CONT
O
DSP ON/OFF control [L: DSP OFF (bypass). H: DSP ON]
MUTE
O
AUDIO_MUTE output [H: Muting ON. L: Muting OFF]
P_ON
O
Internal power control [H: ON. L: OFF]
P_CON
O
External power control [H: ON. L: OFF]
EVOL_DATA
I/O
DATA input/output from/to E_VOL (TDA7400)
EVOL_CLK
O
CLK output to E_VOL (TDA7400)
CD_SW1
I
Input from CDSW1 (Loading start SW)
CD_SW2
I
Input from CDSW2 (12 cm disc detection SW)
CD_SW3
I
Input from CDSW3 (Down & limit SW)
CD_LO/EJ
I/O
CD mechanism loading motor control (LO/EJ) [H: Load. L: Eject]
CD_LMON
O
CD mechanism loading motor control (ON/OFF) [H: Stop. L: Operate]
C_F/R
O
Head switching control [H: Reverse. L: Forward]
CD_MSTOP
O
CD mechanism emergency stop output
CD_MRST
O
CD mechanism reset output
CD_MUTE
I
Muting input from CD mechanism
P_ANT
O
POWER_ANT control [H: Radio mode. L: Other mode]
PLL_CE
O
CE selection to LC72135M
PLL_DO
O
DATA output to LC72135M
PLL_CLK
O
CLK output to LC72135M
PLL_CI
I
DATA input from LC72135M
SW40
O
VFD_Vdd2 control [H: Vdd2 ON. L: Vdd2 OFF]
ILL_CON
O
Button illumination control [H: Illumination ON. L: Illumination OFF]
PWIC_STBY
O
Power IC standby control [H: AMP ON. L: AMP OFF]
PN_MC_REQ
O
Send request output to PNL_µCOM
PN_SC_CON
O
Operation control output to PNL_µCOM
PN_MC_DATA
O
DATA output to PNL_µCOM
PN_SC_DATA
I
DATA input from PNL_µCOM
PN_MC_CLK
O
CLK output to PNL_µCOM
Signal Name
I/O
NC (GND)
I
Not used (GND)
VREF+
I
A/D conver ter reference voltage input terminal
VDD
–
Positive power supply terminal
OSC2
–
Main clock connection (8.38 MHz)
OSC1
–
Main clock connection (8.38 MHz)
VSS
–
Connected to GND
XI
I
Connected to GND
XO
O
Not used (Open)
MMOD
I
Connected to GND
PN_SC_DATA
O
System control communication, data output terminal
x
ao
y
PN_MC_DATA
I
System control communication, data input terminal
i
PN_MC_CLK
I
System control communication, clock input terminal
VFD_DATA
O
VFD driver data output
NC
O
Not used (Open)
VFD_CLK
O
VFD driver clock output
8
Purpose/Description
Q Q
3
6 7
1 3
Purpose/Description
u163
.
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
9 9
Normal Operation
Level
H (a)
H (a)
H (a)
H (a)
H (a)
H (a)
H/L
H/L
L (a)
L (a)
L (a)
H (a)
H (a)
H/L
L (a)
L (a)
L (a)
H (a)
H (a)
H/L
H/L
2 8
9 9
H/L
H (a)
H (a)
H (a)
H (a)
H (a)
H/L
H/L
H/L
Normal Operation
Level
L
–
–
–
–
–
L
–
L
H/L
H/L
H/L
H/L
L
H/L
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