NAD C 521BEE Schematic Diagrams page 10

MAIN BOARD
U302: PCM1710U
MAIN BOARD
U401: M38223E4HP4
Clock Clock
input input
X X
IN OUT
28 29
Clock generating
circuit
X X ø
CIN COUT
Sub- Sub-
clock clock
input output
X
COUT
X
CIN
P7(2) P6(8)
26 27 1 2 3 4 5 6
I/O port P7 I/O port P6
LRCIN
1
Input
Interface
DIN
2
BCKIN
3
CLKO
4
Timing
Control
XTI
5
XTO
6
DGND
7
VDD
8
5-Level DAC
Right
VCC2R
9
AGND2R
10
Low Pass Filter
Right
EXT1R
11
EXT2R
12
CMOS Amp
Right
VOUTR
13
AGND1
14
Reset input
RESET
25
CPU
A
X
Y
S
PC PC
H L
PS
A-D converter(8)
T
OUT
CNTR , CNTR
0 1
RTP , RTP
0
P5(8)
7 8 72 73 9 10 11 12 13 14 15 16 17 18
V
REF
I/O port P5
AV
SS
(0V)
Digital Mode
Filter Control
Noise
Shaper
5-Level DAC
Left
Low Pass Filter
Left
CMOS Amp
Left
(5V) (0V)
Vcc Vss
71 30
Data bus
ROM
Time X(16)
Time Y(16)
Time 1(8) Time 2(8)
Time 3(8)
SI/O(8)
1
P4(8) P3(4)
19 20 21 22 23 24 55 56 57 58
I/O port P4 Input port P3
- 20 -
ML/DSD
28
MC/DM2
27
MC/DM1
26
MUTE
25
MODE
24
CKSL
23
DGND
22
21 VDD
20 VCC2L
19 AGND2L
18 EXT1L
17 EXT2L
16 VOUTL
15 VCC1
RAM
LCD display
RAM
LCD
(16 bytes)
drive control
circuit
P2(8) P1(8)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
I/O port P2 I/O port P1
V
80
L1
V
79
L2
V
78
L3
COM
77
0
COM
76
1
COM
75
2
COM
74
3
SEG
70
0
SEG
69
1
SEG
68
2
SEG
67
3
SEG
66 4
SEG
65
5
SEG
64
6
SEG
63
7
SEG
62
8
SEG
61
9
SEG
60
10
SEG
59
11
P0(8)
48 49 50 51 52 53 54
I/O port P0