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Intel 82555 Datasheet

Intel 10/100 mbps lan physical layer interface
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82555 10/100 Mbps LAN Physical Layer
Interface
Networking Silicon

Product Features

Optimal integration for lower cost solutions
— Integrated 10/100 Mbps single chip
physical layer interface solution
— Complete 10/100 Mbps MII compliance
with MDI support
— Full duplex operation in 10 Mbps and
100 Mbps modes
— IEEE 802.3u Auto-Negotiation support
for 10BASE-T half and full duplex,
100BASE-TX half and full duplex, and
100BASE-T4 configurations
— Parallel detection algorithm for legacy
support of non-Auto-Negotiation
enabled link partner
— Integrated 10BASE-T transceiver with
built in transmit and receive filters
— Glueless interface to T4-PHY for
combination TX/T4 designs with single
magnetics
— Glueless support for 4 LEDs: activity,
link, speed, and duplex
— LED function mapping support via MDI
— Low external component count
— Single 25 MHz clock support for 10
Mbps and 100 Mbps (crystal or
oscillator)
— Single magnetics for 10 Mbps and 100
Mbps operation
— QFP 100-pin package
Notice:
Notice:
Datasheet
Performance enhancements
— Flow control support for IEEE 802.3x
Auto-Negotiation and Bay Technologies
PHY Base* scheme
— Adaptive Channel Equalizer for greater
functionality over varying cable lengths
— High tolerance to extreme noise
conditions
— Very low emissions
— Jabber control circuitry to prevent data
loss in 10 Mbps operation
— Auto-polarity correction for 10BASE-T
— Software compatible with 82557 drivers
Repeater functionality
— Repeater mode operation
— Support for forced speed of 10 Mbps
and 100 Mbps
— Automatic carrier disconnect for IEEE
802.3u compliance
— Auto-Negotiation enable/disable
capability
— Receive port enable function
— Support for 32 configurable addresses
— Narrow analog side (14 mm) for tight
packing in repeater and switch designs
Document Number: 666252-004
Revision 2.0
March 1998

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Summary of Contents for Intel 82555

  • Page 1: Product Features

    82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Product Features Optimal integration for lower cost solutions — Integrated 10/100 Mbps single chip physical layer interface solution — Complete 10/100 Mbps MII compliance with MDI support — Full duplex operation in 10 Mbps and 100 Mbps modes —...
  • Page 2 The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

  • Page 3: Table Of Contents

    10BASE-T Transmit Clock Generation...21 10BASE-T Transmit Blocks ...21 5.2.1 10BASE-T Manchester Encoder...21 5.2.2 10BASE-T Driver and Filter ...21 10BASE-T Receive Blocks ...21 5.3.1 10BASE-T Manchester Decoder...21 5.3.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter...21 Datasheet Networking Silicon — 82555 Contents...
  • Page 4 82555 — Networking Silicon Contents 5.3.3 10BASE-T Error Detection and Reporting ... 22 10BASE-T Collision Detection... 22 10BASE-T Link Integrity ... 22 10BASE-T Jabber Control Function ... 22 10BASE-T Full Duplex ... 23 REPEATER MODE ... 25 Special Repeater Features... 25 Connectivity...

  • Page 5: Introduction

    10/100 Mbps Ethernet controllers and CSMA/CD MAC components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller.
  • Page 6 82555 — Networking Silicon The 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sections. The MAC interface on the 82555 is a superset of the IEEE 802.3u Media Independent Interface (MII) standard.

  • Page 7: Architectural Overview

    Architectural Overview The 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the Media Independent Interface (MII) and the wire through the magnetics. Figure 2 100 Mbps Mode In 100BASE-TX mode the 82555 digital subsection performs all signal processing of digital data obtained from the analog reception and the data to be driven into the analog transmit subsection.

  • Page 8: 10 Mbps Mode

    MII TX Interface 10 Mbps Mode The 82555 operation in 10BASE-T mode is similar to the 82555 operation in 100BASE-TX mode. Manchester encoding and decoding is used instead of 4B/5B encoding/decoding and scrambling/ descrambling. In addition, the Transmit Clock and Receive Clock (MII clock signals) provide 2.5 MHz instead of 25 MHz.

  • Page 9: Media Independent Interface (Mii)

    The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface. Flash (optional) Media Independent Interface (MII) The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC.
  • Page 10 82555 — Networking Silicon Signal Name Transmit Error TXERR (repeater mode only) Table 1. 82555 MII Description Direction From RIC Clock MII Signal Supported Reference by the 82555? Datasheet...

  • Page 11: Pin Definitions

    X2 crystal signals. The transmit differential and receive differential pins are specified as analog outputs and inputs, respectively. The figure below show the pin locations on the 82555 component. The following subsections describe the pin functions. Figure 5. 82555 Pin Numbers and Labels...

  • Page 12: Pin Types

    This type of pin is an output pin from the 82555. This type of pin is both an input and output pin for the 82555. This pin is used as a bias pin. The bias pin is either pulled up or down with a resistor. The bias pin may also be used as an external voltage reference.

  • Page 13: Media Access Control/Repeater Interface Control Pins

    CRS is an asynchronous output signal. Collision Detect. The Collision Detect signal operates in half duplex mode and indicates to the 82555 that a collision has occurred on the link. COL is an asynchronous output signal to the controller.

  • Page 14: Led Pins

    LED driver and will be an active low for all technologies. In repeater mode, this signal is used for Auto-Negotiation advertisement to the 82555’s link partner and activates the PHY Base (Bay Technologies) flow control if 100BASE-TX full duplex is the highest common technology between the 82555 and its link partner.

  • Page 15: Miscellaneous Control Pins

    Type Name and Function Reset. The Reset signal is active high and resets the 82555. A reset pulse width of at least 1 s should be used. This pin is multiplexed and can be used for one of the following: Force 100/10 Mbps.

  • Page 16: Power And Ground Pins

    82555 — Networking Silicon Power and Ground Pins Symbol 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62, 64, 66, 73, 75, 83, 88, 93, 98 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39,...

  • Page 17: 100Base-Tx Adapter Mode Operation

    100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the 82555’s X1 and X2 pins. The 82555 derives its internal transmit digital clocks from this crystal or oscillator input. The Transmit Clock signal is a derivative of the 25 MHz internal clock.

  • Page 18: 100Base-Tx Scrambler And Mlt-3 Encoder

    The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82555 implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation.

  • Page 19: 100Base-Tx Transmit Framing

    Cyclic Redundancy Check (CRC). When TXEN is asserted, the 82555 accepts data on the MII TXD[3:0] lines, encodes it, and sends it out onto the wire. The 82555 encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “TR”...

  • Page 20: Transmit Driver

    Pulse Engineering 100BASE-TX Receive Blocks The receive subsection of the 82555 accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the 82555 will accurately receive valid data from Category 5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters.

  • Page 21: Adaptive Equalizer

    82555 finds the “TR” (“01101, 00111”) and idle symbols in order to de-assert TXDV and CRS. 4.3.5 100BASE-TX Receive Error Detection and Reporting In 100BASE-TX mode, the 82555 can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: •...

  • Page 22: 100Base-Tx Link Integrity And Auto-Negotiation Solution

    PMA level is required and the Auto-Negotiation function of one of the PHYs must be disabled. For this purpose, the 82555 is defined as the master; and the PHY-T4, the slave. In combination mode, only the 82555’s Auto-Negotiation function is enabled (the PHY-T4’s Auto-Negotiation is disabled).

  • Page 23: Auto 10/100 Mbps Speed Selection

    This change takes a maximum of five milliseconds. Adapter Mode Addresses In DTE (adapter) mode, the 82555 supports addresses 0, 1, 2, and 3 through the pins PHYA1 and PHYA0. Four addresses are sufficient in the case of a combination adapter having three PHYs. For switch applications, the T4ADV signal should be de-asserted to allow all 32 addresses to be available in repeater mode.
  • Page 24 82555 — Networking Silicon Datasheet...

  • Page 25: 10Base-T Functionality In Adapter Mode

    10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The 82555 provides the transmit clock and receive clock to the MAC at 2.5 MHz. 10BASE-T Transmit Blocks 5.2.1...

  • Page 26: 10Base-T Error Detection And Reporting

    The link integrity in 10 Mbps works with link pulses. The 82555 senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. In the first and last case, the 82555 activates parallel detection of the respective technology; and in the second case, Auto-Negotiation.

  • Page 27: 10Base-T Full Duplex

    Networking Silicon — 82555 10BASE-T Full Duplex The 82555 supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the 82555 to transmit and receive simultaneously, achieving up to 20 Mbps of network bandwidth. The configuration can be achieved through Auto- Negotiation.
  • Page 28 82555 — Networking Silicon Datasheet...

  • Page 29: Repeater Mode

    Connectivity A 25 MHz buffered oscillator can provide the clock to all of the 82555 devices. A 2.5 MHz (10 Mbps) or a 25 MHz (100 Mbps) signal is required to clock the RIC and the TXC signal in the PHYs.
  • Page 30 PHYs connected to the RIC. Signals TXEN, CRS, and PORTEN are connected from each of the 82555 devices to the specified RIC pin. The figure below illustrates an example of multiple 82555s connected to a 25 MHz (or 2.5 MHz) oscillator.

  • Page 31: Management Data Interface

    MDIO pin; for write cycles, to the 82555. The controller drives addresses and data on the falling edge of the MDC signal, and the 82555 latches the data on the rising edge of the MDC signal. The following list defines protocol terms:...

  • Page 32: Mdi Registers

    82555 — Networking Silicon The 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode. The management frame structure is as follows:...
  • Page 33 0 = Normal operation This bit controls the duplex mode when Auto-Negotiation is disabled. If the 82555 reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the 82555 can operate.
  • Page 34 The Selector Field is a 5-bit field identifying the type of message to be sent via Auto-Negotiation. This field is read only in the 82555 and contains a value of 00001b, IEEE Standard 802.3. Default...
  • Page 35 Datasheet Description This bit reflects the 82555’s link partner’s Auto- Negotiation ability. This bit is used to indicate that the 82555 has successfully received its link partner’s Auto- Negotiation advertising ability. This bit reflects the 82555’s link partner’s Auto- Negotiation ability.
  • Page 36 82555 — Networking Silicon 7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions Bit(s) Name Flow Control Reserved Carrier Sense Disconnect Control Transmit Flow Control Disable Receive De- Serializer In-Sync Indication 100BASE-TX Power-Down 10BASE-T Power-Down Polarity Reserved Speed Duplex Mode 7.2.3.2...
  • Page 37 (such as a symbol error or premature end of frame) in that frame. The counter stops when full (and does not roll over) and self-clears on read. Networking Silicon — 82555 Default Default Default...
  • Page 38 7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions Bit(s) Name 15:0 Jabber Detect Counter 7.2.3.9 Register 27: 82555 Special Control Bit Definitions Bit(s) Name 15:3 Reserved LED Switch Control Description This field contains a 16-bit counter that increments for each symbol error.

  • Page 39: Auto-Negotiation Functionality

    Table 4 set according to what the PHY is capable of supporting. In the case of the 82555, bits 0, 1, 2, and 3 are set. Table 5 lists the priority of each of the technologies.

  • Page 40: Parallel Detect And Auto-Negotiation

    6. Receive FLP from the link partner and record FLP in the MII register Parallel Detect and Auto-Negotiation The 82555 automatically determines the speed of the link either by using Parallel Detect or Auto- Negotiation. Upon a reset, a link status fail, or a negotiate/renegotiate command, the 82555 inserts a long delay during which no link pulses are transmitted.
  • Page 41 Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The 82555 will look for both FLPs and link integrity pulses. The following diagram illustrates this process. Auto-Negotiation capable = 0...
  • Page 42 82555 — Networking Silicon Datasheet...

  • Page 43: Led Descriptions

    Activity: This LED is on (active-low) when activity is detected on the wire. In DTE (adapter) mode, this LED is on during transmit and receive when the 82555 is not in loopback mode. In repeater mode, this LED is on only during receive when the 82555 is not in loopback mode.
  • Page 44 82555 — Networking Silicon Datasheet...

  • Page 45: Reset And Miscellaneous Test Modes

    Test Port When the TESTEN pin is high, the test pins provide a test access port for the 82555. In test mode, the 82555 will default to address 1. The 82555 has a simple Test Access Port (TAP) from which all the test modes are selected and test instructions are operated.
  • Page 46 TCK. The TAP must be reset during power-up. Otherwise, the 82555 can wake-up during high-Z mode or NAND Test, which can be harmful to the board. The TAP should be reset only with a hardware reset input pin and not with software reset. The TOUT control logic selects the TISR output in all tests, except burn-in test modes.

  • Page 47: Electrical Specifications And Timing Parameters

    All input voltages -1.0 Parameter Description Supply voltage 4.75 Case temperature Condition = 4 mA = -4 mA 0 < V < V Condition DC and V /2) + 0.5 V Networking Silicon — 82555 Units Units 5.25 Units 0.45 ±15 Units...

  • Page 48: 100Base-Tx Voltage/Current Dc Characteristics

    82555 — Networking Silicon Symbol Parameter Description Input differential accept voltage IDA10 Input differential reject voltage IDR10 Input common mode voltage ICM10 Output differential voltage OD10 Line driver supply CCT10 Current on all V CC10 Total supply current CCT10TOT Leakage on analog pins ILA10 a.

  • Page 49: Ac Characteristics

    4 0 m A Figure 12. RBIAS100 Resistance versus I Output Levels Figure 13. AC Testing Level Conditions Parameter Conditions 100 Mbps 10 Mbps Networking Silicon — 82555 Units Icct100 4 2 m A CCT100 Input Levels = 2.0 V = 0.8 V...

  • Page 50: Mii Timing Parameters

    82555 — Networking Silicon 1.5V 11.4.2 MII Timing Parameters Symbol TXD[3:0], TXEN, TXERR setup TXDV from the rising edge of TXC TXD[3:0], TXEN, TXERR hold time after the rising edge of TXC RXD[3:0], RXDV, RXERR valid RXSU before the rising edge of RXC...

  • Page 51: Repeater Mode Timing Parameters

    Data Valid Data Invalid Data Valid Figure 17. MII Timing Parameters: MDC/MDIO Parameter Conditions PORTEN RXD[3:0], Signal Driven RXCLK Figure 18. PORT Enable Timing Networking Silicon — 82555 T 1 0 Data Invalid Data Invalid Data Invalid Units clocks clocks...

  • Page 52: Transmit Packet Timing Parameters

    82555 — Networking Silicon 11.4.4 Transmit Packet Timing Parameters Symbol TXC on first TXEN active to start XEN_ST of frame TXC on first TXEN active to start T15a XEN_ST of frame TXC on first TXEN active to XEN_CRSH rising edge of CRS...

  • Page 53: Jabber Timing Parameters

    Figure 20. Squelch Test Timing Parameters Parameter Conditions 10 Mbps 10 Mbps TXEN C O L Figure 21. Jabber Timing Parameters Parameter Conditions 100 Mbps 10 Mbps 100 Mbps 10 Mbps 100 Mbps Networking Silicon — 82555 Units Units bits bits bits bits bits...

  • Page 54: 10Base-T Normal Link Pulse (Nlp) Timing Parameters

    82555 — Networking Silicon Symbol End of receive frame to falling T26a R_CRSL edge of CRS End of receive frame to falling R_RXDVL edge of RXDV End of receive frame to falling T27a R_RXDVL edge of RXDV Frame On link 11.4.8...

  • Page 55: Reset Timing Parameters

    FLP Burst width FLP burst period Clock Pulse Data Pulse Figure 24. Fast Link Pulse Timing Parameters Parameter Conditions Power Up (VCC) RESET Figure 25. Reset Timing Parameters Parameter Conditions ±50 PPM Networking Silicon — 82555 Units Clock Pulse Units Units...

  • Page 56: 100Base-Tx Transmitter Ac Specification

    82555 — Networking Silicon 11.4.12 100BASE-TX Transmitter AC Specification Symbol TDP/TDN differential output peak jitter 4.0V 2.5V 0.4V Figure 26. X1 Clock Specifications Parameter Conditions HLS data Units Datasheet...

  • Page 57: 82555 Package Information

    12.0 82555 Package Information This section provides the physical packaging information for the 82555. The 82555 is an 100-pin plastic Quad Flat Pack (QFP) device. Package attributes are provided in are shown in Figure Datasheet Seating Plane See Detail A Figure 27.

  • Page 58: Datasheet

    82555 — Networking Silicon Table 7. Dimensions for the 82555 QFP Symbol Description Lead Angle Coplanarity Norm 10.0 0.10 Datasheet...

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