Ic Block Diagrams & Signal Description - NAD T 562 Service Manual

IC BLOCK DIAGRAMS & SIGNAL DESCRIPTION
1. U5 (V8601VWA
SIGNAL DESCRIPTION
Signal I/O Pins
Front End
DSYNC I 213
DREQ O 214
DCLK I 215
DSTB I 216
DVD[7:0] I *
External I/O
PCS0 O 193
XIO[14:1] B
SDRAM
MD[31:0] B *
MA[11:0] O *
MA[13:12] O 32-33
MCLK O 22
CKE O 24
CS0- O 35
CS1- O 66
RAS- O 37
CAS- O 38
WE- O 39
DQM[3:0]- O 11, 41,42, 65
Host Interface
AD[31:0] B *
LA[3:0] B 184-187
ALE B 183
RD- B 189
ACK- B 161
SCLK O 160
PWE[3:0]- B *
Slave Mode
LHLD I 191
LHLDA O 190
DVD DSP)
Description
DVD parallel mode Sector Sync
DVD parallel mode Data Request
Data sampling clock
Parallel mode Data Valid, serial mode Left/Right Clock
DVD drive parallel data port, pins: 217, 219-223, 225, 226
Peripheral chip select 0, generally used for enabling the program store ROM/FLASH
Programmable general purpose I/O also used as peripheral chip select, interrupt, PWM output and other system
signals, pins: 195, 197-200, 202-203, 205-209, 211
SDRAM data bus, pins: 227, 229, 231, 232, 234, 235, 236, 238, 239, 240, 2, 3, 5, 7, 8, 9, 43, 45
46, 48, 50, 51, 52, 54, 55, 56, 58, 59, 60, 61, 63, 64
SDRAM address bus, pins: 12, 13, 15, 16, 18, 20, 21, 25, 26, 28, 29, 30
SDRAM address bus, reserved for pin compatibility with 64Mbit SDRAM
SDRAM clock
SDRAM Clock Enable
SDRAM primary bank chip select
SDRAM extension bank chip select
SDRAM command bit
SDRAM command bit
SDRAM command bit
SDRAM data byte enables
P multiplexed address/data bus, pins: 136-139, 141-144, 146, 148-153, 155, 157, 158, 163-168, 172-176, 78-180
Latched Address [3:0]
Address Latch Enable
Read
Programmable WAIT-/ACK-/RDY- control
External bus clock used for programmable host bus peripherals
Byte write enable for FLASH, EEPROM, SRAM or peripherals, pins: 145, 156, 170, 182
Bus Hold Request from external master in slave mode
Bus Hold Acknowledge in slave mode
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