Aiwa XP-V311 Service Manual page 14

IC DESCRIPTION
IC, LC78641NE-D
Pin No. Pin Name
1 PDO1
2 PDO2
3 VVSS
4 PCKIST
5 VVDD
6 FR
7 HFL
8 SLCIST
9 SLCO
10 EFMIN
11 JITTV
12 JITTC
13 BH
14 PH (RFENV)
15 FE
16 TE
17 VREF
18 ADAVDD
19 ADAVSS
20 PHREF
21 BHREF
22 TBLO
23 TDO
24 FDO
25 SPDO
26 SLDO
27 DVREF/FG
28 LASER
29 CONT1
30 CONT2
31 CONT3
32 CONT4
33 CONT5
34 PCK
35 C2F
36 VDD
I/O
O Internal VCD control phase comparator output pin.
Internal VCD control phase comparator output pin. OFF for rough servo, ON for phase
O
servo.
— Internal VCD ground pin.
I PDO output current adjustment resistor connection pin. (pull up)
Internal VCD power supply pin. (2000pF or more path controller to be inserted at a
—
point nearer to the pin between this pin and GND)
I VCD frequency range adjustment resistor connection pin. (pull up)
I Mirror detection signal input pin.
I SLCO output current adjustment resistor connection pin. (pull up)
O Control outout.
I EFM signal input pin.
O Jitter detection monitor pin.
O Jitter detection adjustment pin.
I BH signal input pin. A/D input. (Must be connected to OV when unused)
I PH signal or RFENV signal input pin. A/D input.
I FE signal input pin. A/D input.
I TE signal input pin. A/D input.
I VREF input pin. A/D input.
Servo A/D, D/A power supply pin. (2000pF or more path controller to be inserted at a
—
point nearer to the pin between this pin and GND)
— Servo A/D, D/A ground pin.
O PH reference output pin. D/A output.
O BH reference output pin. D/A output.
O Tracking balance output pin. D/A output.
O Tracking control output pin. D/A output.
O Focus control output pin. D/A output.
O Spindle control output pin. D/A output.
O Thread control output pin. D/A output.
Output driver VREF output pin. Input FG signal input pin. (Must be connected to OV
I/O
when unused)
O Laser ON/OFF control pin.
I/O General-purpose input/output pin 1.
I/O General-purpose input/output pin 2.
I/O General-purpose input/output pin 3.
I/O General-purpose input/output pin 4.
I/O General-purpose input/output pin 5.
O EFM data playback clock monitor pin. Average 4.3218MHz when the phase is locked.
O C2 flag output pin.
Digital power supply pin. (2000pF or more path controller to be inserted at a point
—
nearer to the pin between this pin and GND)
16
Description