Yamaha DVD-S1700 Service Manual page 20

DVD-S1700
Symbol Type
Pin.
1 H_A[1] IN
2 H_DQ[15] I/O10
3 H_DQ[14] I/O10
4 GND_IO1 GND_IO
5 H_DQ[13] I/O10
6 H_DQ[12] I/O10
7 H_DQ[11] I/O10
8 H_DQ[10] I/O10
9 H_DQ[9] I/O10
10 VCC_IO1 VCC_IO1
11 H_DQ[8] I/O10
12 H_DQ[7] I/O10
13 H_DQ[6] I/O10
14 H_DQ[5] I/O10
15 H_DQ[4] I/O10
16 H_DQ[3] I/O10
17 GND_IO2 GND_IO
18 H_procclock IN
19 VCC_Core1 VCC_core
20 GND_Core1 GND_core
21 sys_clk IN
22 H_DQ[2] I/O10
23 H_DQ[1] I/O10
24 H_CSn IN
25 H_DQ[0] I/O10
26 H_RWn IN
27 H_WAIT O10
28 H_IRQn O10
29 aud_clk IN
30 PCM_dclk_in IN
31 PCM_wclk_in IN
32 V VDDCO
DDA
33 V VSSCO
SSA
34 biasin APIO
35 Agcinp APIO
36 Adcrefl APIO
37 V _IO7 VCC_IO
CC
38 GND_IO7 GND_IO
39 PCM_CeLf_in IN
40 PCM_LeRi_in IN
41 PCM_LsRs_in IN
42 B_FLAG/SERR IN
43 B_SYNC/Sync IN
44 B_WCLK/SENB IN
45 B_DATA/Be_dat(0) IN
46 B_BCLK/SDCLK IN
47 UDE_req IN
48 Data_req O10
49 Be_dat(1) IN
50 Be_dat(2) IN
51 Be_dat(3) IN
52 Be_dat(4) IN
53 Be_dat(5) IN
54 Be_dat(6) IN
55 Be_dat(7) IN
56 TRST IN1
57 TMS IN1
58 VCC_IO2 VCC_IO
59 TDO O10
60 TDI IN1
61 TCK IN
62 H_sel[0] IN
63 H_sel[1] IN
20
[1]
Description
Address bus
Data bus
Data bus
GND I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Vcc_I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
GND I/O pads
Host processor EMI interface clock
Core supply voltage
Core ground
System clock
Data bus
Data bus
Host chip select; active LOW
Data bus
Read = 1; Write = 0
Wait signal
Interrupt request; active LOW
DSD audio clock
PCM data clock
PCM word clock
V of ADC
DD
V of AGC and ADC;
SS
Connected to substrate
Bias current input
AGC positive input signal; HF in
ADC decoupling
VCC I/O pads
GND I/O pads
PCM data center or LFE
PCM data left or right
PCM data left or right surround
I 2 S-bus flag (EDC flag)
Sector sync or absolute time sync
2
I S-bus word clock or UDE data
sense from host
2
I S-bus data or LSB data of parallel interface
2
I S-bus bit clock
Host request data from front-end;
routed via the SAA7893HL
Data request for UDE
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Boundary scan reset
Boundary scan mode select
V I/O pads
CC
Output
Boundary scan data input
Boundary scan clock
Host select signals: SAD16,
MAD16 and SAD08
Host select signals: SAD16,
MAD16 and SAD08
Symbol Type[1]
Pin
64 D_ADDR[3] O10
65 D_ADDR[4] O10
66 D_ADDR[2] O10
67 D_ADDR[5] O10
68 D_ADDR[1] O10
69 GND_IO3 GND_IO
70 D_ADDR[6] O10
71 D_ADDR[0] O10
72 D_ADDR[7] O10
73 D_ADDR[10] O10
74 D_ADDR[8] O10
75 D_ADDR[13] O10
76 VCC_IO3 VCC_IO
77 D_ADDR[9] O10
78 D_ADDR[12] O10
79 D_ADDR[11] O10
80 D_Wen O10
81 D_RASn O10
82 D_CASn O10
83 GND_IO4 GND_IO
84 GND_Core2 GND_core
85 VCC_Core2 VCC_core
86 D_clk O10
87 D_DQ[5] I/O10
88 D_UDQM O10
89 D_LDQM O10
90 D_DQ[7] I/O10
91 D_DQ[8] I/O10
92 VCC_IO4 VCC_IO
93 D_DQ[6] I/O10
94 D_DQ[9] I/O10
95 D_DQ[10] I/O10
96 D_DQ[4] I/O10
97 D_DQ[11] I/O10
98 D_DQ[3] I/O10
99 GND_IO5 GND_IO
100 D_DQ[12] I/O10
101 D_DQ[2] I/O10
102 D_DQ[13] I/O10
103 D_DQ[1] I/O10
104 D_DQ[14] I/O10
105 D_DQ[0] I/O10
106 VCC_IO5 VCC_IO
107 D_DQ[15] I/O10
108 DSD_PCM_0 O10
109 DSD_PCM_1 O10
110 DSD_PCM_2 O10
111 DSD_PCM_3 O10
112 GND_IO6 GND_IO
113 DSD_PCM_4 O10
114 DSD_PCM_5 O10
115 DSD_PCM_6 O10
116 DSD_PCM_7 O10
117 DSD_PCM_8 O10
118 VCC_IO6 VCC_IO
119 DSD_PCM_10 O10
120 DSD_PCM_9 O10
121 DSD_PCM_11 O10
122 RESETn IN
123 H_A_sel IN
124 H_A[6] IN
125 H_A[5] IN
126 H_A[4] IN
127 H_A[3] IN
128 H_A[2] IN
Description
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
GND I/O pads
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
Vcc I/O pads
SDRAM address bus
SDRAM address bus
SDRAM address bus
Read or write
Row address select; active LOW
Column address select; active LOW
GND I/O pads
Core ground
Core supply voltage
Clock signal needed for SDRAM
Data bus
DQ mask enable (upper)
DQ mask enable (lower)
Data bus
Data bus
Vcc I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
GND I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Vcc_IO pads
Data bus
6-channel data output
6-channel data output
6-channel data output
6-channel data output
GND I/O pads
6-channel data output
6-channel data output
6-channel data output
6-channel data output
2-channel data output
V I/O pads
CC
2-channel data output
2-channel clock or control
2-channel data output
Asynchronous reset; active LOW
Address select
Address bus
Address bus
Address bus
Address bus
Address bus