Related Manuals for Kodak KAI-4011
Summary of Contents for Kodak KAI-4011
- Page 1 USERS MANUAL Revision 4.0 MTD/PS-0521 December 1, 2005 KODAK KAI-4011 / KAI-4021 IMAGER EVALUATION BOARD...
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Page 2: Table Of Contents
Table 4: Clock Voltages...................................5 Table 5: J1 Interface Connector Pin Assignments ........................8 FIGURES Figure 1: KAI-4011/KAI-4021 Imager Board Block Diagram ......................6 Figure 2: Measured Performance -- Linearity ..........................7 Figure 3: Measured Performance -- Dynamic Range and Noise Floor..................7 ©Eastman Kodak Company, 2005 www.kodak.com/go/imagers... -
Page 3: Description
KAI-4011/KAI-4021 Imager Evaluation Board, The KAI-4011/KAI-4021 Imager Board has been designed referred to in this document as the Imager Board, is to operate the KAI-4011/KAI-4021 CCDs with the designed to be used as part of a two-board set, used in specified performance at 40MHz pixel clocking rate and conjunction with a Timing Generator Board. -
Page 4: Architecture Overview
ARCHITECTURE OVERVIEW The following sections describe the functional blocks of the KAI-4011/KAI-4021 Imager board (refer to Figure 1). once per frame to transfer the charge from the POWER FILTERING AND REGULATION photodiodes to the vertical CCDs. Power is supplied to the Imager Board via the J1 CCD FDG DRIVER interface connector. -
Page 5: Operational Settings
The following clock voltage levels are fixed, or adjusted with a potentiometer as noted. The nominal values listed in Table 4 were correct at the time of this document’s publication, but may be subject to change; refer to the KAI-4011/KAI-4021 device specification. -
Page 6: Block Diagram And Performance Data
CCD SENSOR FDG CKT VES CKT DRIVER DRIVER DRIVER DRIVER DRIVER LVDS TO TTL BUFFERS +15V REGULATOR LVDS RECEIVERS -15V REGULATOR J1 BOARD INTERFACE CONNECTOR Figure 1: KAI-4011/KAI-4021 Imager Board Block Diagram ©Eastman Kodak Company, 2005 www.kodak.com/go/imagers Revision 4.0 (MTD/PS-0521) p6... -
Page 7: Figure 2: Measured Performance -- Linearity
Noise floor = 3.65 counts (33.9 electrons) LVSAT = 30220 electrons VSAT = 32980 electrons 1000 10000 100000 Signal Mean (Electrons) Figure 3: Measured Performance -- Dynamic Range and Noise Floor ©Eastman Kodak Company, 2005 www.kodak.com/go/imagers Revision 4.0 (MTD/PS-0521) p7... -
Page 8: Connector Assignments And Pinouts
AGND AGND AMP_ENABLE+ AMP_ENABLE- -5V_MTR -5V_MTR N.C. N.C. AGND AGND N.C. N.C. +5V_MTR +5V_MTR N.C. N.C. AGND AGND N.C. N.C. VPLUS_MTR VPLUS_MTR N.C. N.C. Table 5: J1 Interface Connector Pin Assignments ©Eastman Kodak Company, 2005 www.kodak.com/go/imagers Revision 4.0 (MTD/PS-0521) p8... -
Page 9: Warnings And Advisories
KAI-4011 and KAI-4021 CCD image sensors. Purchasers of a Kodak Evaluation Board Kit may, at their discretion, make changes to the Timing Generator Board firmware. Eastman Kodak can only support firmware developed and supplied by Eastman Kodak. Changes to the firmware are at the risk of the customer. -
Page 10: Appendices
APPENDICES KAI-4011/KAI-4021 IMAGER BOARD SCHEMATICS ©Eastman Kodak Company, 2005 www.kodak.com/go/imagers Revision 4.0 (MTD/PS-0521) p10... - Page 28 ©Eastman Kodak Company, 2005. Kodak and Pixelux are trademarks.