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2 System Board - (SiS Chipset) (Part Number: D4051-63001)
Devices on the Processor Local Bus (D4051-63001)
Level-1 Cache Memory
The L1 cache memory is divided into two separate banks:
• L1 I-cache for instruction words.
• L1 D-cache for data words.
For more information about Level-1 cache, refer to "Instruction and Data
Cache" on page 46.
Level-2 Cache Memory
The L2 cache memory, when installed, has a 32-byte line size. It is controlled
by the Host Bridge chip (SiS 5511) in the system board chipset. A single HP
cache memory module consists of 256 KB of direct mapped, synchronous,
static random access memory (SRAM).
Pentium Processor (D4051-63001)
The Pentium processor uses 64-bit architecture and is 100% compatible
with Intel's family of x86 processors. All application software that has been
written for Intel386 and Intel486 processors can run on the Pentium without
modification. The Pentium processor contains all the features of the
Intel486 processor, with the following added features which enhance
performance:
• Superscalar Architecture
• Floating Point Unit
• Dynamic Branch Prediction
• Instruction and Data cache
• Data Integrity
• Supports MultiProcessor Specification (MPS) 1.1
• PCI bus architecture
• Advanced Power Management capability for reducing power consumption
The processor is seated in a Zero Insertion Force (ZIF) socket.
45
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