IBM System x3500 M3 Product Manual page 6

A rock-solid, performance server for your most demanding
applications
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Regardless of memory speed, the Xeon 5600/5500 platform represents a significant improvement in
memory bandwidth over the previous Xeon 5400 platform. At 1333MHz, the improvement is almost
500% over the previous generation. This huge improvement is mainly due to the dual integrated
memory controllers and faster DDR-3 1333MHz memory. Throughput at 800MHz is 25 gigabytes
per second (GBps); at 1066MHz it's 32GBps; and at 1333MHz it's 35GBps. This improvement
translates into improved application performance and scalability.
Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A
balanced system provides the best interleaving. A Xeon 5600/5500 processor-based system is
balanced when all memory channels on a socket have the same amount of memory.
A memory rank is simply a segment of memory that is addressed by a specific address bit. DIMMs
typically have 1, 2 or 4 memory ranks, as indicated by their size designation.
• A typical memory DIMM description is 2GB 4Rx8 DIMM
• The 4R designator is the rank count for this particular DIMM (R for rank = 4)
• The x8 designator is the data width of the rank
It is important to ensure that DIMMs with appropriate number of ranks are populated in each
channel for optimal performance. Whenever possible, it is recommended to use dual-rank
DIMMs in the system. Dual-rank DIMMs offer better interleaving and hence better performance than
single-rank DIMMs. For instance, a system populated with six 2GB dual-rank DIMMs outperforms a
system populated with six 2GB single-rank DIMMs by 7% for SPECjbb2005. Dual-rank DIMMs are
also better than quad-rank DIMMs because quad-rank DIMMs will cause the memory speed to
be down-clocked.
Another important guideline is to populate equivalent ranks per channel. For instance, mixing one
single-rank DIMM and one dual-rank DIMM in a channel should be avoided.
Note: It is important to ensure that all three memory channels in each processor are populated. The
relative memory bandwidth decreases as the number of channels populated decreases. This is
because the bandwidth of all the memory channels is utilized to support the capability of the
processor. So, as the channels are decreased, the burden to support the requisite bandwidth is
increased on the remaining channels, causing them to become a bottleneck.
For increased availability, the x3500 M3 offers an additional (but mutually exclusive) level of IBM
Active Memory protection: online memory mirroring.
Memory mirroring works much like disk mirroring. The total memory is divided into two channels.
Data is written concurrently to both channels. If a DIMM fails in one of the DIMMs in the primary
channel, it is instantly disabled and the mirrored (backup) memory in the other channel becomes
active (primary) until the failing DIMM is replaced. One-half of total memory is available for use with
mirroring enabled. (Note: Due to the double writes to memory, performance is affected.)
Mirroring is handled at the hardware level; no operating system support is required.
DDR3 memory is currently available in 1GB, 2GB, 4GB, 8GB and 16GB RDIMMs, or 1GB, 2GB,
4GB UDIMMs. DIMMs are installed individually (not in pairs). However, for performance reasons, in
a 2-processor system, it's best to install matching DIMMs for each processor.
Maximum memory capacity and speed in 2-processor configurations include:
DIMMs per
Memory Frequency
Channel
1333MHz
(6 DIMMs)
1333MHz
(12 DIMMs)
1066MHz
(12 DIMMs)
800MHz
(16 DIMMs)
Max.
Memory
Capacity
96GB
E5645, E5647,
1 RDIMM;
E5649, X5650
24GB
UDIMM
192GB
E5645, E5647,
2 RDIMM;
E5649, X5650
48GB
UDIMM
192GB
2 RDIMM;
E5607, E5620
48GB
UDIMM
192GB
3
RDIMM;
48GB
UDIMM
5600 Series 5500 Series
N/A
and above
N/A
and above
E5603 –
E5520 and
above
and above
E5620 and E5502 - E5507
above and above
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