Sony HCD-FC8 Service Manual page 92

HCD-FC8/FC9
Pin No. Pin Name
VDDE
46
WMD1
47
VSS
48
WMD0
49
50 PAGE2
VSS
51
52, 53 PAGE1, PAGE0
BOOT
54
BTACT
55
BST
56
MOD1
57
MOD0
58
EXLOCK
59
VDDI
60
VSS
61
A17, A16
62, 63
A15 to A13
64 to 66
GP10
67
68 GP9
GP8
69
70 VDDI
VSS
71
D15 to D12
72 to 75
VDDE
76
D11 to D8
77 to 80
VSS
81
A9, A12 to A10
82 to 85
TDO
86
TMS
87
88 XTRST
TCK
89
90 TDI
VSS
91
A8 to A3
92 to 97
D7, D6
98, 99
VDDI
100
VSS
101
102 to 105 D5 to D2
106 VDDE
D1, D0
107, 108
109, 110 A2, A1
VSS
111
112 A0
PM
113
92
I/O
—
Power supply terminal (+3.3V)
I
S-RAM wait mode setting terminal Fixed at "H" in this set
—
Ground terminal
I
S-RAM wait mode setting terminal Fixed at "H " in this set
O Page selection signal output terminal Not used
—
Ground terminal
O Page selection signal output terminal Not used
I
Boot mode control signal input terminal Not used
O
Boot mode state display signal output terminal Not used
I
Boot strap signal input from the system controlle r
PLL input frequency selection signal input terminal
I
"L": 384fs, "H": 256fs (fixed at "H" in this set)
I
Mode setting terminal
I
PLL lock error and data error flag input from the digital audio interface IC
—
Power supply terminal (+2.6V)
—
Ground terminal
O
Address signal output terminal Not used
O
Address signal output to the S-RAM
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
O Decode signal output to the system controller
I
Bit 1 input terminal of channel status from the digital audio interface IC
— Power supply terminal (+2.6V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
—
Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
—
Ground terminal
O
Address signal output to the S-RAM
O
Simple emulation data output terminal Not used
I
Simple emulation data input start/end detection signal input terminal Not used
I Simple emulation asychronous break input terminal Not used
I
Simple emulation clock signal input terminal Not used
I Simple emulation data input terminal Not used
—
Ground terminal
O
Address signal output to the S-RAM
I/O
Two-way data bus with the S-RAM
—
Power supply terminal (+2.6V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
O Address signal output to the S-RAM
—
Ground terminal
O Address signal output to the S-RAM
I
PLL reset signal input from the system controller "L": reset
Description
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)