LG 32LC7D Service Manual page 37

1.8V Regulator for HD2.4 Digital Power 1
+3.3V
IC400
AZ1117H-1.8TRE1(EH13A)
+1.8V_HD2_DIGITAL_D1 +1.8V_HD2_DIGITAL_D1
INPUT 3 1ADJ/GND
2
OUTPUT OUTPUT
C400 C402 $0.06
10uF 10uF 0.1uF
25V 16V
L401
MLB-201209-0120P-N2 MLB-201209-0120P-N2
C405
C407
0.1uF 0.1uF 10uF
16V 25V
VH_HS VH_HS
VH_VS
HS_TO_ADC HS_TO_ADC
VH_FID VH_FID
HD2_EXT_CLK R448 0
AD21
DVI_DE DVI_DE 1/16W EXT_HD
5% AC21
R408 EXT_VD
DVI_DE_OUT AE21
OPT ORG_HD
AF22 EXT_INFIELD
AF8
VH_C/B[0-9] VH_C/B[0-9] EXT_CLK
AE22
EXT_DVI_DE
1.8V Regulator for HD2.4 Digital Power 2 1.8V Regulator for HD2.4 Digital Power 2 AF26
VH_C/B[0] VH_C/B[0] EXT_DB0
VH_C/B[1] VH_C/B[1] AE25
VH_C/B[0-9] VH_C/B[0-9] EXT_DB1
VH_C/B[2] VH_C/B[2] AF25
EXT_DB2
VH_C/B[3] VH_C/B[3] AD24 EXT_DB3
VH_C/B[4] VH_C/B[4] AE24
EXT_DB4
VH_C/B[5] VH_C/B[5] AF24
EXT_DB5
+3.3V VH_C/B[6] VH_C/B[6] AD23 EXT_DB6
VH_Y/G[0-9] VH_Y/G[0-9] AE23
VH_C/B[7] VH_C/B[7] EXT_DB7
VH_C/B[8] VH_C/B[8] AF23
EXT_DB8
IC404 VH_C/B[9] VH_C/B[9] AD22
VH_Y/G[0-9] EXT_DB9
AZ1117H-1.8TRE1(EH13A) AA24
VH_Y/G[0] VH_Y/G[0] EXT_DG0
+1.8V_HD2_DIGITAL_D2 +1.8V_HD2_DIGITAL_D2 VH_Y/G[1] VH_Y/G[1] AB26
INPUT EXT_DG1
3 1ADJ/GND VH_Y/G[2] VH_Y/G[2] AB25
EXT_DG2
2 VH_Y/G[3] VH_Y/G[3] AB24 EXT_DG3
AC26
C492 OUTPUT OUTPUT VH_Y/G[4] VH_Y/G[4] EXT_DG4
C490 $0.06 VH_C/R[0-9] VH_C/R[0-9] VH_Y/G[5] VH_Y/G[5] AC25
10uF 10uF 0.1uF EXT_DG5
25V 16V VH_Y/G[6] VH_Y/G[6] AC24
AD26 EXT_DG6
VH_Y/G[7] VH_Y/G[7] EXT_DG7
L404 VH_Y/G[8] VH_Y/G[8] AD25
EXT_DG8
VH_Y/G[9] VH_Y/G[9] AE26
EXT_DG9
MLB-201209-0120P-N2 MLB-201209-0120P-N2
VH_C/R[0] VH_C/R[0] W26 EXT_DR0
VH_C/R[1] VH_C/R[1] W25
C489 C491 EXT_DR1
0.1uF 0.1uF 10uF VH_C/R[2] VH_C/R[2] W24
25V EXT_DR2
16V VH_C/R[3] VH_C/R[3] W23 EXT_DR3
Y26
VH_C/R[0-9] VH_C/R[0-9] VH_C/R[4] VH_C/R[4] EXT_DR4
VH_C/R[5] VH_C/R[5] Y25
EXT_DR5
VH_C/R[6] VH_C/R[6] Y24
EXT_DR6
VH_C/R[7] VH_C/R[7] Y23 EXT_DR7
VH_C/R[8] VH_C/R[8] AA26
EXT_DR8
VH_C/R[9] VH_C/R[9] AA25
EXT_DR9
R491
A2
4.7K D1CLK
R499 0 A4
VH_TP/D1_CLK VH_TP/D1_CLK CHACLK(TP_STROB)
A12
VH_TP/D1_VALID VH_TP/D1_VALID CHA_VALID
B12 CHA_ERROR
TP_ERROR C12
TP_SOP TP_SOP CHA_SOP/PESREQ
VH_TP/D1_DATA[0] VH_TP/D1_DATA[0] C13
CHA/D1_0
VH_TP/D1_DATA[1] VH_TP/D1_DATA[1] AR406 AR406 B13
VH_TP/D1_DATA[2] VH_TP/D1_DATA[2] A13 CHA/D1_1
0 CHA/D1_2
VH_TP/D1_DATA[3] VH_TP/D1_DATA[3] A14
CHA/D1_3
VH_TP/D1_DATA[4] VH_TP/D1_DATA[4] B14
CHA/D1_4
VH_TP/D1_DATA[5] VH_TP/D1_DATA[5] AR407 C14 CHA/D1_5
VH_TP/D1_DATA[6] VH_TP/D1_DATA[6] 0 A15
CHA/D1_6
VH_TP/D1_DATA[7] VH_TP/D1_DATA[7] B15
CHA/D1_7
R493 4.7K
A11 TP_PWM
AF20
VCR_PWM
AF21
VH_TP/D1_DATA[0-7] VH_TP/D1_DATA[0-7] MAIN_PWM MAIN_PWM MAIN_PWM
HD2_SYSCLK V1
R405 R405 SYSCLK
0
0 R406 R406
1/16W J3
0 5% 1/16W R407 R407 XREQ/AUDIO_REQ
J2 XSTRB/AUDIO_STROBE
LDATA[0-31] LDATA[0-31] 5% 1/16W K4
5% XDATA/AUDIO_DATA
LDATA[0-31] LDATA[0-31]
LDATA[0] LDATA[0] B11 HOSTDATA0
C11
LDATA[1] LDATA[1] HOSTDATA1
D11
LDATA[2] LDATA[2] HOSTDATA2
LDATA[3] LDATA[3] A10
HOSTDATA3
LDATA[4] LDATA[4] B10 HOSTDATA4
C10
LDATA[5] LDATA[5] HOSTDATA5
D10
LDATA[6] LDATA[6] HOSTDATA6
LDATA[7] LDATA[7] A9
B9 HOSTDATA7
LDATA[8] LDATA[8] HOSTDATA8
C9
LDATA[9] LDATA[9] HOSTDATA9
LDATA[10] LDATA[10] D9
HOSTDATA10
LDATA[11] LDATA[11] A8 HOSTDATA11
B8
LDATA[12] LDATA[12] HOSTDATA12
C8
LDATA[13] LDATA[13] HOSTDATA13
LDATA[14] LDATA[14] D8
HOSTDATA14
LDATA[15] LDATA[15] C7 HOSTDATA15
B4
LDATA[16] LDATA[16] HOSTDATA16
LDATA[17] LDATA[17] C4
HOSTDATA17
LDATA[18] LDATA[18] B3 HOSTDATA18
A1
LDATA[19] LDATA[19] HOSTDATA19
B2
LDATA[20] LDATA[20] HOSTDATA20
3.3V Regulator for HD2.4 LDATA[21] LDATA[21] C3
HOSTDATA21
LDATA[22] LDATA[22] B1 HOSTDATA22
C2
LDATA[23] LDATA[23] HOSTDATA23
C1
LDATA[24] LDATA[24] HOSTDATA24
+6.0V +6.0V LDATA[25] LDATA[25] D3 HOSTDATA25
D2
LDATA[26] LDATA[26] HOSTDATA26
D1
LDATA[27] LDATA[27] HOSTDATA27
LDATA[28] LDATA[28] E3
IC402 IC402 HOSTDATA28
LDATA[29] LDATA[29] E2 HOSTDATA29
AZ1117H-3.3 E1
LDATA[30] LDATA[30] HOSTDATA30
LADDR[1-12] LADDR[1-12] F4
INPUT ADJ/GND +3.3V_HD2 LADDR[1-12] LADDR[1-12] LDATA[31] LDATA[31] HOSTDATA31
3 1ADJ/GND
OUTPUT F3
LADDR[1] LADDR[1] HOSTADDR1
C401 C401 C403 F2
0.1uF 0.1uF 2 LADDR[2] LADDR[2] HOSTADDR2
22uF $0.06 L400 LADDR[3] LADDR[3] F1
35V 16V 16V HOSTADDR3
LADDR[4] LADDR[4] G4 HOSTADDR4
MLB-201209-0120P-N2 MLB-201209-0120P-N2 G3
C404 C406 LADDR[5] LADDR[5] HOSTADDR5
22uF 0.1uF 0.1uF G2
LADDR[6] LADDR[6] HOSTADDR6
35V 16V LADDR[7] LADDR[7] G1
HOSTADDR7
LADDR[8] LADDR[8] H4 HOSTADDR8
H3
LADDR[9] LADDR[9] HOSTADDR9
LADDR[10] LADDR[10] H2
HOSTADDR10
+3.3V_HD2 LADDR[11] LADDR[11] H1 HOSTADDR11
J4
LADDR[12] LADDR[12] HOSTADDR12
B7
R409 HOSTREADYPOL
0 R446 D7 HOSTTYPE1
10K R447 D6
0 1/16W 1/16W HOSTTYPE0 For ARM
5% A7
HC_RDY HC_RDY 1/16W 1/16W HOSTREADY
5% A6 HOSTWR
CH_WR B6
CH_CS HOSTCS
R492 R492 22 C6
CH_STRB CH_STRB HOSTDSTB
R450 OPT A5
HD2_DMAACK1 HD2_DMAACK1 DMAACK
B5 DMAREQ
HC_DREQ HC_DREQ R411 0 C5
IRQ
HC_IRQ HC_IRQ R412 100 A3
CPU_CLKOUT CPU_CLKOUT HOSTCLK
R451 0
R400 22 HD2_DMAACK2 HD2_DMAACK2 C15
HD2_TDO TDO
R401 22 A16
BST_TRST TRST
R402 22 B16
BST_TCK TCK
R403 22 C16 TMS
BST_TMS R404 22 D16
TDI
CPU_TDO CPU_TDO
FOR BOUNDARY SCAN TEST T4
TESTSE
T3
TESTMODE0
U3
TESTMODE1
U4 TESTMODE2
1.8V Digital Power
+1.8V_HD2_DIGITAL_D1 +1.8V_HD2_DIGITAL_D1
+1.8V_HD2_DIGITAL_D2 +1.8V_HD2_DIGITAL_D2
THE THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SYMBOL MARK OF THE SCHEMETIC.
16V
LDATA[0-31] LDATA[0-31] LDATA[0-31]
LADDR[2-24]
LADDR[2-24] 3.3VDD_FLASH 3.3VDD_SDRAM
IC200
0.1uF C204 VDD1
MX29LV320CTTC-70G
LDATA[0] DQ0
LADDR[17] A15 A16 LADDR[18] 0.1uF C205 VDDQ1
1 48
LDATA[1] DQ1
LADDR[16] A14 BYTE#
2 47
LDATA[2] DQ2
LADDR[15] A13 GND_2
3 46
VSSQ1
+3.3V LADDR[14] A12 Q15/A-1 LDATA[15]
4 45
LDATA[3] DQ3
LADDR[13] A11 Q7 LDATA[7]
5 44 LDATA[4] DQ4
LADDR[12] A10 Q14 LDATA[14]
6 43
VDDQ2
LADDR[11] A9 Q6 LDATA[6] 0.1uF C206
7 42
LDATA[5] DQ5
LADDR[10] A8 Q13 LDATA[13]
8 41
LDATA[6] DQ6
LADDR[21] A19 Q5 LDATA[5]
9 40
LADDR[22] A20 Q12 LDATA[12] VSSQ2
10 39
LDATA[7] DQ7
WE# Q4 LDATA[4]
11 38
R220 VDD2
4.7K RESET# VCC 0.1uF C207
12 37
OPT LDQM
LADDR[23] R219 0 NC Q11 LDATA[11] DQM0/WBE0
13 36
WE
WP#/ACC Q3 LDATA[3] CPU_WE
R220 R219 14 35 CAS
RY/BY# Q10 LDATA[10]
15 34 SCAS
4MB 4.7K OPT RAS
LADDR[20] A18 Q2 LDATA[2]
16 33 SRAS
8MB OPT 0 CS
LADDR[19] A17 Q9 LDATA[9]
17 32 SCS0
LADDR[22] R211 0 BA0
LADDR[9] A7 Q1 LDATA[1]
18 31 R212
LADDR[8] Q8 LDATA[8] LADDR[23] 0 R213 0 BA1
A6 19 30
LADDR[12] A10/AP
LADDR[7] A5 Q0 LDATA[0]
20 29
LADDR[2] A0
LADDR[6] A4 OE#
21 28
LADDR[3] A1
LADDR[5] A3 GND_1
22 27
LADDR[4] A2
LADDR[4] A2 CE#
23 26 LADDR[5] A3
LADDR[3] A1 A0 LADDR[2]
24 25
VDD3
0.1uF C208
R214
LADDR[24] 0
R209
0
FLASH_DOWN
R211
8MB
16MB OPT
CPU_WE
SYS_RESET
CPU_OE
FLASH_CS
3.3VDD_FLASH 3.3VDD_SDRAM
IC201 VDD1
0.1uF C209
MX29LV320CTTC-70G LDATA[16] DQ0
0.1uF VDDQ1 C210
LADDR[17] A15 A16 LADDR[18]
1 48 LDATA[17] DQ1
LADDR[16] BYTE#
A14 2 47 LDATA[18] DQ2
LADDR[15] A13 GND_2
3 46 VSSQ1
+3.3V
LADDR[14] A12 Q15/A-1 LDATA[31]
4 45 LDATA[19] DQ3
LADDR[13] A11 Q7 LDATA[23]
5 44 LDATA[20] DQ4
LADDR[12] A10 Q14 LDATA[30]
6 43 0.1uF C211 VDDQ2
LADDR[11] A9 Q6 LDATA[22]
7 42 LDATA[21] DQ5
LADDR[10] A8 Q13 LDATA[29]
8 41 LDATA[22] DQ6
LADDR[21] A19 Q5 LDATA[21]
9 40 VSSQ2
LADDR[22] A20 Q12 LDATA[28]
10 39 LDATA[23] DQ7
R221 Q4 LDATA[20]
WE# 11 38 VDD2
4.7K 0.1uF C212
RESET# VCC
12 37 LDQM
OPT
LADDR[23] NC Q11 LDATA[27] DQM2/WBE2
R222 0 13 36 WE
R221 R222
WP#/ACC Q3 LDATA[19] CPU_WE
14 35 CAS
4MB 4.7K OPT SCAS
RY/BY# Q10 LDATA[26]
15 34 RAS
8MB OPT 0 LADDR[20] A18 Q2 LDATA[18] SRAS
16 33 CS
LADDR[19] A17 Q9 LDATA[25] SCS0
17 32 LADDR[22] BA0
R215 0
LADDR[9] A7 Q1 LDATA[17] R216
18 31 LADDR[23] 0 R217 0 BA1
LADDR[8] A6 Q8 LDATA[24]
19 30 LADDR[12] A10/AP
LADDR[7] Q0 LDATA[16]
A5 20 29 LADDR[2] A0
LADDR[6] A4 OE#
21 28 LADDR[3] A1
LADDR[5] A3 GND_1
22 27 LADDR[4] A2
LADDR[4] A2 CE#
23 26 LADDR[5] A3
LADDR[3] A1 A0 LADDR[2]
24 25 0.1uF C213 VDD3
R218
LADDR[24] 0
R215
8MB
C PU MEMORY(FLASH/SDRAM) 16MB OPT
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
HD2_MEM_DATA[0-63]
HD2_MEM_BA1
HD2_MEM_BA0
HD2_MEM_CS
HD2_MEM_WE
HD2_MEM_RAS
HD2_MEM_CAS
HD2_MEM_CLK2 HD2_MEM_CLK2
HD2_MEM_CLK1 HD2_MEM_CLK1
HD2_MEM_ADDR[0-11] HD2_MEM_ADDR[0-11]
DOUT_G13
DOUT_G12
DOUT-G11
DOUT_G10
DOUT_G9
DOUT_G8
DOUT_G7
DOUT_G6
DOUT_G5
DOUT_G4
DOUT_G3
DOUT_G2
VCR_D1_DATA5/DOUT_G1 VCR_D1_DATA5/DOUT_G1
VCR_D1_DATA4/DOUT_GO
DOUT_R13 DOUT_R13
DOUT_R12 DOUT_R12
IC401 DOUT_R11 DOUT_R11
DOUT_R10 DOUT_R10
DOUT_R9 DOUT_R9
DOUT_R8 DOUT_R8
DOUT_R7 DOUT_R7
DOUT_R6 DOUT_R6
DOUT_R5 DOUT_R5
DOUT_R4 DOUT_R4
DOUT_R3 DOUT_R3
DOUT_R2 DOUT_R2
VCR_D1_DATA1/DOUT_R1
VCR_D1_DATA0/DOUT_R0
DOUT_B13 DOUT_B13
DOUT_B12 DOUT_B12
DOUT_B11 DOUT_B11
LGDT1102F (HD2.4)
DOUT_B10 DOUT_B10
DOUT_B9 DOUT_B9
DOUT_B8 DOUT_B8
DOUT_B7 DOUT_B7
DOUT_B6 DOUT_B6
DOUT_B5 DOUT_B5
DOUT_B4 DOUT_B4
DOUT_B3 DOUT_B3
DOUT_B2 DOUT_B2
VCR_D1_DATA3/DOUT_B1
VCR_D1_DATA2/DOUT_B0 VCR_D1_DATA2/DOUT_B0
VCR_D1_DATA6
(HD 2.4)
VCR_D1_DATA7
DOUT_DE DOUT_DE
DOUT_CLK
DOUT_HACTIVE
DOUT_VACTIVE
DOUT_FIELD
NT2CLK
VDPCLK VDPCLK
DAC_AVSSB
AVSSIO_CVBS
DAC_AVSSG DAC_AVSSG
3.3V Analog Ground
DAC_AVSSR
DAC_VSSG DAC_VSSG
DAC_AVSS DAC_AVSS
DAC_AVD33B DAC_AVD33B
AVDDIO_CVBS
DAC_AVD33G DAC_AVD33G
3.3V Analog Power
$ 14.5 DAC_AVD33R DAC_AVD33R
DAC_AVD33 DAC_AVD33
DAC_VDDG DAC_VDDG
DVSS_DAC DVSS_DAC
AVSSIO_PLL
PLL_AVSS
1.8V Analog Ground PLL_DVSS PLL_DVSS
AUPLL_AVSS2
AUPLL_DVSS AUPLL_DVSS
AUPLL_AVSS
AVSSIO_AUPLL AVSSIO_AUPLL
DVDD_DAC
AVDDIO_PLL AVDDIO_PLL
PLL_AVDD PLL_AVDD
1.8V Analog Power PLL_DVDD PLL_DVDD
AUPLL_AVDD2
AUPLL_DVDD
AUPLL_AVDD
AVDDIO_AUPLL
SVIDEO_C
SVIDEO_Y SVIDEO_Y
CVBS_OUT CVBS_OUT
COMP
RSET
VREFOUT
VREFIN VREFIN
AUDCLK
SPDIF_CLK
AUDCLK_OUT
SYNCLK
FSEL
EXT_RESETN
EXT_DAC_LRCK EXT_DAC_LRCK
EXT_DAC_SCK EXT_DAC_SCK
IEC958_OUT IEC958_OUT
IEC958LRCH
CDLRCH
CDLRCK
CDSCK
DACLRCH DACLRCH
DACSLRCH DACSLRCH
DACCLFCH DACCLFCH
DACSELLRCH
DACHLRCH DACHLRCH
LINELRCH LINELRCH
LINELRCK LINELRCK
LINESCK LINESCK
MICLRCH MICLRCH
MICLRCK MICLRCK
MICSCK
1.8V Digital Ground 3.3V Digital Power
STANDBYMODE
3.3V Digital Ground
+3.3V_HD2 +3.3V_HD2
3.3VDD_SDRAM
IC202
HY57V641620ETP-6
VSS3
1 54
DQ15 LDATA[15]
2 53
3 52 VSSQ4
DQ14 LDATA[14]
4 51
DQ13 LDATA[13]
5 50
VDDQ4 0.1uF C214
6 49
DQ12 LDATA[12]
7 48
DQ11 LDATA[11]
8 47
VSSQ3
9 46
DQ10 LDATA[10]
10 45
DQ9 LDATA[9]
11 44
12 43 VDDQ3 0.1uF C215
DQ8 LDATA[8]
13 42
VSS2 +3.3V 3.3VDD_FLASH
14 41
NC
15 40
UDQM
16 39 DQM1/WBE1
CLK L200
17 38
SCLK
CKE MLB-201209-0120P-N2
18 37
SCKE
A12 C218 C220 C222
19 36 0.01uF
0.1uF
A11 LADDR[13] 47uF 16V
20 35
21 34 A9 LADDR[11]
A8 LADDR[10]
22 33
A7 LADDR[9]
23 32
A6 LADDR[8]
24 31
A5 LADDR[7]
25 30
A4 LADDR[6]
26 29
VSS1
27 28
+3.3V 3.3VDD_SDRAM
R213 R212 R214 L201
MLB-201209-0120P-N2
0 0 OPT OPT
OPT 00 C219 C221 C223
0.1uF 0.01uF
47uF 16V
3.3VDD_SDRAM
IC203
HY57V641620ETP-6
VSS3
1 54
DQ15 LDATA[31]
2 53
VSSQ4
3 52
DQ14 LDATA[30]
4 51
DQ13 LDATA[29]
5 50
VDDQ4
6 49 0.1uF C216
DQ12 LDATA[28]
7 48
DQ11 LDATA[27]
8 47
9 46 VSSQ3
DQ10 LDATA[26]
10 45
DQ9 LDATA[25]
11 44
VDDQ3 0.1uF C217
12 43
DQ8 LDATA[24]
13 42
VSS2
14 41
NC
15 40
UDQM
16 39 DQM3/WBE3
CLK
17 38 SCLK
18 37 CKE
SCKE
A12
19 36
A11 LADDR[13]
20 35
A9 LADDR[11]
21 34
A8 LADDR[10]
22 33
A7 LADDR[9]
23 32
A6 LADDR[8]
24 31
A5 LADDR[7]
25 30
A4 LADDR[6]
26 29
27 28 VSS1
R217 R216 R218
VH_EXT_CLK OPT R210 HD2_EXT_CLK
0 0 OPT OPT
OPT 0 0
0Delay BUF
07AUS_BASIC 2006. 12.02
FLASH/SDRAM/0Delay BUF
HD2_MEM_DATA[0-63] HD2_MEM_DATA[0-63]
TUNER
1.8V Regulator for HD2.4 Analog Power
+3.3V
HD2_MEM_ADDR[0-11]
+6.0V
IC403
AZ1117H-1.8TRE1(EH13A) AZ1117H-1.8TRE1(EH13A)
+1.8V_HD2_ANALO +1.8V_HD2_ANALOG
INPUT 3 1ADJ/GND
2
OUTPUT
C484 C485
22uF 0.1uF
16V
16V
L402
MLB-201209-0120P-N2
C486
C487
0.1uF 47uF
16V 16V
XDR_DATA_G[0-9] XDR_DATA_G[0-9]
AR400
AE20 22 XDR_DATA_G[9] XDR_DATA_G[9]
AC19
XDR_DATA_G[8] XDR_DATA_G[8]
AD19
XDR_DATA_G[7] XDR_DATA_G[7]
AE19 XDR_DATA_G[6] XDR_DATA_G[6]
AF19 AR401 22 XDR_DATA_G[5] XDR_DATA_G[5]
AC18
XDR_DATA_G[4] XDR_DATA_G[4]
AD18 XDR_DATA_G[3] XDR_DATA_G[3]
AE18 XDR_DATA_G[2] XDR_DATA_G[2]
AF18 AF18 R415 22
XDR_DATA_G[1] XDR_DATA_G[1]
AC17 R416 22
XDR_DATA_G[0] XDR_DATA_G[0]
AD17
AE17
AF17
AD16
XDR_DATA_R[0-9]
AE16 AR402 22
XDR_DATA_R[9]
AF16
XDR_DATA_R[8]
AD15 XDR_DATA_R[7]
AE15 XDR_DATA_R[6]
AF15 AR403
22 XDR_DATA_R[5]
AF14
XDR_DATA_R[4]
AE14 XDR_DATA_R[3]
AD14 XDR_DATA_R[2]
AF13 R413 22
XDR_DATA_R[1]
AE13 R414 22 XDR_DATA_R[0]
AD13 +1.8V_HD2_ANALOG
AF12
XDR_DATA_B[0-9]
AE12
AD12
+3.3V_HD2
AR404
AF11
22 XDR_DATA_B[9]
AE11 XDR_DATA_B[8]
AD11 XDR_DATA_B[7]
AF10 AF10
XDR_DATA_B[6]
AE10 AR405
22 XDR_DATA_B[5]
AD10 XDR_DATA_B[4]
AC10 XDR_DATA_B[3]
AF9
XDR_DATA_B[2]
AE9 R417 22 XDR_DATA_B[1]
AD9 R418 22 XDR_DATA_B[0] C467 C483 C493
AC9 10uF
10uF 0.1uF
AD8 25V 25V 16V
AC8
AC7
R432
AD20
0 XDR_CLK_OUT_LVDS XDR_CLK_OUT_LVDS
AC20
AE6
R431 33 XDR_DE_OUT
AF7
AE7 R433 33
AD7 XDR_HS_OUT
R434 33 XDR_VS_OUT R452
AF6 0
R435 22 XDR_FID_OUT XDR_FID_OUT XDR_CLK_OUT_CPLD
AE8
HD2_NT2CLK
U1
HD2_VDPCLK
AE5
AE4
AE3
AE2
AC3
AB3
AD5 C469
0.01uF
AD4 C470 0.01uF
AD3 C471 0.01uF
AD2
C472 0.01uF
AC2 C473 0.01uF
AC1 C474 0.01uF
AC6
AB2
AA4
AA3
Y4
Y3
W4
W3
AD6 C475 0.01uF
AB1 C476
0.01uF
AA2 C477
0.01uF
AA1 C478 0.01uF
Y2 C479 0.01uF
Y1 C480
0.01uF
W2 C481 0.01uF
W1 C482 0.01uF
AF5
AF4
AF3
DTV_CVBS DTV_CVBS
AF1 C464 0.01uF
AE1 R436 182
AF2 C465
0.01uF
AD1
R437 OPT
+3.3V_HD2
T1
R1 R498 33
HD2_SPDIF_CLK
T2 C488 HD2_DAC_MCLK
V2 R494 FSEL
OPT
V4 4.7K
Low : MEMCLK=135MHz Low : MEMCLK=135MHz
U2
HD2_RESET
High : MEMCLK=162MHz
R495 +3.3V_HD2
4.7K
R3 R423
22 HD2_DAC_LRCLK
R2 R424 22
HD2_DAC_SCLK
N1 R425 22 HD2_ICE958_OUT
M1 R426
0 HD2_ICE958_IN
M2 R420 OPT
M3 R421 1K TO MSP4440
L1
R422 1K
P3 R427 22
HD2_DAC_LRCH
P2
P1 R496 +3.3V_HD2
N3
4.7K
N2
L2 R428 22
AUDIO_IN_DATA_H
L3 R429 0 AUDIO_IN_LRCLK FROM MSP4440
K1 R430 0
AUDIO_IN_SCLK
K2 R497 OPT
K3
J1
V3 R444 OPT PWR_DOWN
+3.3V 3.3VDD_CPLD
L300
MLB-201209-0120P-N2
C300 C301 C302
0.01uF
0.1uF
47uF 16V
3.3VDD_CPLD
0 R3003
I2C_HUB_EN4
0 R3004
I2C_HUB_EN3
0 R3005
I2C_HUB_EN2
0 R3006
I2C_HUB_EN1
I2C_HUB0
I2C_HUB1
0.1uF
0 R3002
DET_SPDIF
CV_SYNC_MODE1
CV_SYNC_MODE0
22 R3007
EPLD_TDO
CH_STRB
CH_CS
CPU_OE
0.1uF
CPU_WE
CPU_WAIT
R3000
CH_WR
OPT 22 R3008
0
R3009
HC_RDY 0
R3010
0
R3011
22 R3012
RX_HDMI_SPDIF
22 R3013
HD2_ICE958_OUT
22 R3014
PWR_DOWN
22 R3015
SPDIF_BYPASS_SEL
22 R3016
CPU_CLKOUT
OPT R3017
HD2_SPDIF_CLK
0.1uF
22 R3018
SPDIF_OUT
22 R3019
SYS_RESET
CPLD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
2 15
D800 +5V_TU
C
AC
A
KDS226
C817 C819
R808 10K 1000pF 10uF
COFDM/PAL 50V 16V
L800
VIN 3 VOUT TU800
MLB-201209-0120P-N2 1
C800 C802 IC800
2 VC
47uF 0.1uF NC PQ05DZ1U TDFC-G106P
16V 16V 4 C806
0.1uF
16V
5
GND
B1_A5 OPT
R823
1
B2_5V
2
AGC
3 C820 OPT
R814
0.01uF
GND0 OPT
4
+5V_TU +3.3V_TU
B3_5V
5
IC802
VT
AZ1117H-3.3
6
INPUT ADJ/GND
3 1
AFT
0.01uF
2 7 R813 OPT C816
OUTPUT C811
C810 0.1uF
0.1uF VIDEO_OUT OPT
8
AUDIO_OUT
9
SIF
10
TU_IF
11
SCLT
+1.8V_TU
+3.3V +3.3V_TU 12
SDAT C814
C 13 18pF OPT
AC
A
L810 L801 B4_1.8V C818
120-ohm 120-ohm D801 18pFOPT
14
OPT KDS226
IC801 B5_3.3V
AZ1117H-1.8TRE1(EH13A) 15
INPUT 3 1 ADJ/GND
GND1
2 16
C804
C803
47uF 0.1uF SW
OUTPUT
16V 17
C805
0.1uF
RST
18
SYNC
R821
19
22
VAL
20 R822
22
D0
21
VH_TP/D1_DATA[0]
SPLITTER VH_TP/D1_DATA[1]
D1
VH_TP/D1_DATA[2]
22
VH_TP/D1_DATA[3]
D2
AR801
23 22
D3
24
J800
KCN-BT-0-0055
D4
25
VH_TP/D1_DATA[4]
1 D5 VH_TP/D1_DATA[5]
26 VH_TP/D1_DATA[6]
VH_TP/D1_DATA[7]
2
D6
AR800
BOOSTER_OFF 22
27
3
D7
28
4
SDA
29
SCL C813 18pF
30 OPT
ERR C815 18pF
31 OPT
MCL
32
33
SHIELD
3.3VDD_CPLD
JP6
4.7K R3075
EPLD_TDI
JP7
4.7K R3076
EPLD_TMS
JP8
4.7K R3077
EPLD_TCK
JP9
4.7K R3078
EPLD_TDO
C348
100pF
C349 100pF
C309 C310
OPT OPT
CPU or MICOM SEL
C303
GND
VCCIO 109 72
I/O
I/O 110 71
I/O
I/O 111 70
I/O
I/O 112 69
I/O 0
I/O 113 68 R3079
GND 114 TCK 22 R3080
IO4_6 76 50 IO3_4 67
I/O 115 I/O
IO4_7 77 49 IO3_3 66
I/O 116 TMS 22 R3081
IO4_14 78 48 TCK 65
I/O 117 I/O
IO4_18 79 IC300 47 TMS 64
I/O 118 TDI 22 R3082
NC9 80 46 NC7 63
I/O 119 GND
IO4_10 81 45 TDI 62
I/O 120 XC95288XL-10TQ I/O 22 R3083
IO4_12 82 44 GND3 61
I/O 121 I/O
TDO 83 43 NC6 60
TDO 122 I/O 22 R3084
GND7 84 $1.93 42 IO3_9 59
GND 123 I/O 22 R3085
IO4_13 85 41 IO3_1 58
I/O 124 I/O 10pF C322
IO4_16 86 40 IO1_18 57
I/O 125 I/O OPT C323
IO2_1 87 39 IO1_16 56
I/O 126 55 VCCIO 0.1uF C315 10pF C324
C304 VCCIO_2.5V/3.3V_4 88 VCCIO_2.5V/3.3V_2 38
VCCIO 127 I/O 22 R3086
IO4_15 89 37 IO3_8 54
I/O 128 I/O 22 R3087
IO4_17 90 36 IO1_13 53
I/O 129 I/O 22 R3088
IO2_3 91 35 IO3_5 52
I/O 130 I/O 22 R3089
IO2_18 92 34 NC5 51
I/O 131 IC305 50 I/O 22 R3090
IO2_4 93 33 IO1_12
I/O 132 49 I/O 22 R3091
IO2_2 94 32 IO3_2
I/O 133 XC9572XL-10TQ100C 48 I/O 22 R3092
IO2_5 95 31 GND2
I/O 134 OPT 47 GND 15pF OPT R3093
IO2_6 96 30 IO1_17 100
I/O 135 46 I/O C318
IO2_8 97 29 IO1_15
I/O 136 $0.8 45 I/O 22 R3094
VCCINT_3.3V_3 98 28 IO1_10
I/O 137 44 I/O 22 R3095
IO2_9/GSR 99 IO1_14/GCK3 27
I/O 138 43 I/O
GND8 100 VCCIO_2.5V/3.3V_1 26
I/O 139 42 VCCINT 0.1uF C316
I/O 140 41 I/O 22
C305
VCCINT 141 40 I/O 22
I/O 142 39 I/O 22
I/O/GSR 143 38 I/O/GCK3
GND 144 37 VCCIO 0.1uF C317
OPT R3035
C312 C313 C314
OPT OPT OPT
SYMBOL MARK OF THE SCHEMETIC.
+5V_TU
+1.8V_TU +3.3V_TU
C831 C832 C834 C836
+5V_TU C833 C837
C821 C824 C827 C828 16V 10uF 220uF
1000pF 10uF 220uF 1000pF 16V
220uF
220uF 10uF 1000pF
16V 16V 16V
50V
L805
FI-C2012-682KJT
C830
0.01uF
SIF
C829 E
0.01uF
Q807
2SA1504S
B
C
C823 +5V_TU
OPT
25V 4.7uF
10V
L804
MLB-201209-0120P-N2
R839
R835 0
M_TU_CVBS
OPT
L808
3.3uH
OPT
E components locate
R832
0
2SA1504S
Q804
B far from tuner
C
R828
0
SCL_CH1
R829
0
SDA_CH1
R841
OPT
22
TUNER_RESET
R840
22
SYS_RESET
C825
TP_SOP 1000pF
50V
3:K5
VH_TP/D1_VALID
+5V_TU +3.3V_TU
2K
R851
Q808
47K
BSS83
R853
SCL_CH4
SCL_CH4_1
2K
R852
VH_TP/D1_DATA[0-7]
Q809
47K
BSS83
R854
R836 22 SDA_CH4 SDA_CH4_1
SDA_CH4_1
R837 22
SCL_CH4_1
R833
22
TP_ERROR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
R834
22
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
VH_TP/D1_CLK
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V R3129
OPT
C
OPT B Q300
R3126 KRC102S
E
P300
OPT SYS_RESET
R3127 GIL-G-06-S3T2
OPT
R3128 CPU_RESET
C335 C337
OPT OPT 22 R3140 1
EPLD_TCK
IC304
74HC14D 22 R3141 2
EPLD_TDO
R3100 R3109
330 I O 100 A1 VCC
1 3 1 14 C345
3
2 0 Y1 A6 100pF
R3120 2 13
G IC301
C331 A2 Y6
C325 KIA7029AF 10uF 3 12 EPLD_TMS 22 R3142 4
10uF 16V
16V 0 R3121 Y2 A5
SYS_RESET 4 11
A3 Y5 EPLD_TDI 22 R3143 5
5 10
0 R3122 Y3 A4
CPU_RESET 6 9
6
GND Y4
7 8
H/W RESET CPLD_Download
+5V_ST 3.3VST_MICOM +5.0V
0.33uF C329
DVIRGB_HS_POL
EPLD_TCK
C334
IC303 47uF
EPLD_TMS ST3232CDR 16V
10
0.047uF C326 C1+ VCC 5
EPLD_TDI 1 16
9
C347 0.33uF V+ GND 4
2 15
VH_FID 100 8
C1- T1OUT DEBUG_TxD0 R3132
3 14 3
100 7
VH_VS C2+ R1IN DEBUG_RxD0 R3133
4 13
VH_HS 2
0.33uF C327 C2- R1OUT C333 C336 6
5 12 330pF 330pF
1
V- T1IN
6 11
KCN-DS-1-0088
T2OUT T2IN CN300
DVI_DE 7 10 0 R3123
DVI_VS R2IN R2OUT
8 9 0 R3124 22 R3136 EPLD_TCK
DVI_HS
0
DVI_DE_OUT R3125 22 R3137 EPLD_TDO
0
XDR_DE_OUT R3112
22 R3138 EPLD_TMS
XDR_FID_OUT 0.33uF C330
XDR_DE_OUT2 22 R3139 EPLD_TDI
$ 0.38 CPU_RxD0
CPU_TxD0
XDR_CLK_OUT_CPLD
XDR_HS_OUT UCOM_RX
XDR_VS_OUT
R3096 OPT
AV1_S_SW
R3097 OPT
AV1_V_SW
R3098 OPT
AV2_V_SW
RS232(UART)
+5.0V +3.3V +3.3V +3.3V +5.0V
IC302
PA9516APW
0
R3107 SCL0 VCC
CPU_SCL 1 16
0
R3108 SDA0 EN4
CPU_SDA 2 15 I2C_HUB_EN4
SCL1 SDA4
SCL_CH1 3 14 SDA_CH4
SDA1 SCL4
SDA_CH1 4 13 SCL_CH4
EN1 5 12 EN3
I2C_HUB_EN1 I2C_HUB_EN3
SCL2 6 11 SDA3
SCL_CH2 SDA_CH3
SDA2 7 10 SCL3
SDA_CH2 SCL_CH3
GND 8 9 EN2
I2C_HUB_EN2
$ 0.85
I2C 2 TO 4 HUB